SBOS351E March   2006  – December 2015 OPA2333 , OPA333

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information: OPA333
    5. 6.5 Thermal Information: OPA2333
    6. 6.6 Electrical Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Operating Voltage
      2. 7.3.2 Input Voltage
      3. 7.3.3 Internal Offset Correction
      4. 7.3.4 Achieving Output Swing to the Op Amp Negative Rail
      5. 7.3.5 DFN Package
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 High-Side Voltage-to-Current (V-I) Converter
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
      2. 8.2.2 Precision, Low-Level Voltage-to-Current (V-I) Converter
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
      3. 8.2.3 Composite Amplifier
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Detailed Design Procedure
        3. 8.2.3.3 Application Curve
    3. 8.3 System Examples
      1. 8.3.1 Temperature Measurement Application
      2. 8.3.2 Single Operational Amplifier Bridge Amplifier Application
      3. 8.3.3 Low-Side Current Monitor Application
      4. 8.3.4 Other Applications
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 General Layout Guidelines
      2. 10.1.2 DFN Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Related Links
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

See (1)
MIN MAX UNIT
Voltage Supply 7 V
Signal input terminals(2) –0.3 (V+) + 0.3
Current Signal input terminals(2) –1 1 mA
Output short-circuit(3) Continuous
Operating junction temperature, TJ 150 °C
Operating temperature, TA –40 150
Storage temperature, Tstg –65 150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.3 V beyond the supply rails should be current limited to 10 mA or less.
(3) Short-circuit to ground, one amplifier per package.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±4000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
Supply voltage, VS 1.8 5.5 V
Specified temperature –40 125 °C

6.4 Thermal Information: OPA333

THERMAL METRIC(1) OPA333 UNIT
D (SOIC) DBV (SOT) DCK (SC70)
8 PINS 5 PINS 5 PINS
RθJA Junction-to-ambient thermal resistance 140.1 220.8 298.4 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 89.8 97.5 65.4 °C/W
RθJB Junction-to-board thermal resistance 80.6 61.7 97.1 °C/W
ψJT Junction-to-top characterization parameter 28.7 7.6 0.8 °C/W
ψJB Junction-to-board characterization parameter 80.1 61.1 95.5 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance — — — °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Thermal Information: OPA2333

THERMAL METRIC(1) OPA2333 UNIT
D (SOIC) DGK (VSSOP) DRB (VSON)
8 PINS 8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 124.0 180.3 46.7 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 73.7 48.1 26.3 °C/W
RθJB Junction-to-board thermal resistance 64.4 100.9 22.2 °C/W
ψJT Junction-to-top characterization parameter 18.0 2.4 1.6 °C/W
ψJB Junction-to-board characterization parameter 63.9 99.3 22.3 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance — — 10.3 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.6 Electrical Characteristics

At TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE
VOS Input offset voltage VS = 5 V 2 10 μV
dVOS/dT Input offset voltage drift TA = –40°C to 125°C 0.02 0.05 μV/°C
PSRR Power-supply rejection ratio VS = 1.8 V to 5.5 V, TA = –40°C to 125°C 1 5 μV/V
Long-term stability(1) See note (1) µV
Channel separation, dc 0.1 μV/V
INPUT BIAS CURRENT
IB Input bias current TA= 25°C ±70 ±200 pA
TA = –40°C to 125°C ±150
IOS Input offset current ±140 ±400
NOISE
Input voltage noise f = 0.01 Hz to 1 Hz 0.3 μVPP
f = 0.1 Hz to 10 Hz 1.1
in Input current noise f = 10 Hz 100 fA/√Hz
INPUT VOLTAGE
VCM Common-mode voltage range (V–) – 0.1 (V+) + 0.1 V
CMRR Common-mode rejection ratio (V–) – 0.1 V < VCM < (V+) + 0.1 V,
TA = –40°C to 125°C		 106 130 dB
INPUT CAPACITANCE
Differential 2 pF
Common-mode 4 pF
OPEN-LOOP GAIN
AOL Open-loop voltage gain (V–) + 100 mV < VO < (V+) – 100 mV,
RL = 10 kΩ, TA = –40°C to 125°C		 106 130 dB
FREQUENCY RESPONSE
GBW Gain-bandwidth product CL = 100 pF 350 kHz
SR Slew rate G = +1 0.16 V/μs
OUTPUT
Voltage output swing from rail RL = 10 kΩ 30 50 mV
RL = 10 kΩ, TA = –40°C to 125°C 70
ISC Short-circuit current ±5 mA
CL Capacitive load drive See Typical Characteristics
Open-loop output impedance f = 350 kHz, IO = 0 A 2 kΩ
POWER SUPPLY
VS Specified voltage range 1.8 5.5 V
IQ Quiescent current per amplifier IO = 0 A 17 25 μA
TA = –40°C to 125°C 28
Turn-on time VS = +5 V 100 μs
TEMPERATURE
TA Specified range –40 125 °C
Operating range –40 150 °C
Tstg Storage range –65 150 °C
(1) 300-hour life test at 150°C demonstrated randomly distributed variation of approximately 1 μV.

6.7 Typical Characteristics

Table 1. List of Typical Characteristics

TITLE FIGURE
Offset Voltage Production Distribution Figure 1
Offset Voltage Drift Production Distribution Figure 2
Open-Loop Gain vs Frequency Figure 3
Common-Mode Rejection Ratio vs Frequency Figure 4
Power-Supply Rejection Ratio vs Frequency Figure 5
Output Voltage Swing vs Output Current Figure 6
Input Bias Current vs Common-Mode Voltage Figure 7
Input Bias Current vs Temperature Figure 8
Quiescent Current vs Temperature Figure 9
Large-Signal Step Response Figure 10
Small-Signal Step Response Figure 11
Positive Overvoltage Recovery Figure 12
Negative Overvoltage Recovery Figure 13
Settling Time vs Closed-Loop Gain Figure 14
Small-Signal Overshoot vs Load Capacitance Figure 15
0.1-Hz to 10-Hz Noise Figure 16
Current and Voltage Noise Spectral Density vs Frequency Figure 17
At TA = 25°C, VS = 5 V, and CL = 0 pF, unless otherwise noted.
OPA333 OPA2333 tc_histo_bos351.gif
Figure 1. Offset Voltage Production Distribution
OPA333 OPA2333 tc_oloop-frq_bos351.gif
Figure 3. Open-Loop Gain and Phase vs Frequency
OPA333 OPA2333 tc_psrr-frq_bos351.gif
Figure 5. Power-Supply Rejection Ratio vs Frequency
OPA333 OPA2333 tc_ib-vcm_bos351.gif
Figure 7. Input Bias Current vs Common-Mode Voltage
OPA333 OPA2333 tc_iq-tmp_bos351.gif
Figure 9. Quiescent Current vs Temperature
OPA333 OPA2333 tc_resp_sm_bos351.gif
Figure 11. Small-Signal Step Response
OPA333 OPA2333 tc_neg_recov_bos351.gif
Figure 13. Negative Overvoltage Recovery
OPA333 OPA2333 tc_ovrshoot-cl_bos351.gif
Figure 15. Small-Signal Overshoot
vs Load Capacitance
OPA333 OPA2333 tc_noise-frq_bos351.gif
Figure 17. Current and Voltage Noise Spectral Density vs Frequency
OPA333 OPA2333 tc_histo_drift_bos351.gif
Figure 2. Offset Voltage Drift Production Distribution
OPA333 OPA2333 tc_cmrr-frq_bos351.gif
Figure 4. Common-Mode Rejection Ratio vs Frequency
OPA333 OPA2333 tc_vos-io_bos351.gif
Figure 6. Output Voltage Swing vs Output Current
OPA333 OPA2333 tc_ib-tmp_bos351.gif
Figure 8. Input Bias Current vs Temperature
OPA333 OPA2333 tc_resp_lg_bos351.gif
Figure 10. Large-Signal Step Response
OPA333 OPA2333 tc_pos_recov_bos351.gif
Figure 12. Positive Overvoltage Recovery
OPA333 OPA2333 tc_tim-cloop_bos351.gif
Figure 14. Settling Time vs Closed-Loop Gain
OPA333 OPA2333 tc_noise_bos351.gif
Figure 16. 0.1-Hz to 10-Hz Noise