SBOSAC9D august   2022  – april 2023 OPA2992-Q1 , OPA4992-Q1 , OPA992-Q1

PRODMIX  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information for Single Channel
    5. 6.5 Thermal Information for Dual Channel
    6. 6.6 Thermal Information for Quad Channel
    7. 6.7 Electrical Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Protection Circuitry
      2. 7.3.2 EMI Rejection
      3. 7.3.3 Thermal Protection
      4. 7.3.4 Capacitive Load and Stability
      5. 7.3.5 Common-Mode Voltage Range
      6. 7.3.6 Phase Reversal Protection
      7. 7.3.7 Electrical Overstress
      8. 7.3.8 Overload Recovery
      9. 7.3.9 Typical Specifications and Distributions
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Low-Side Current Measurement
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
        1. 9.1.1.1 TINA-TI (Free Software Download)
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

GUID-75CC0A3E-CFF7-4CC9-99A8-725FE366032B-low.svgFigure 5-1 OPA992-Q1 DBV Package,
5-Pin SOT-23
(Top View)
GUID-F2F50B6A-DE12-4FC5-B55F-40FCC64B43C0-low.svgFigure 5-2 OPA992-Q1 DCK Package,
5-Pin SC70
(Top View)
Table 5-1 Pin Functions: OPA992-Q1
PIN TYPE(1) DESCRIPTION
NAME SOT-23 SC70
IN+ 3 1 I Noninverting input
IN– 4 3 I Inverting input
OUT 1 4 O Output
V+ 5 5 — Positive (highest) power supply
V– 2 2 — Negative (lowest) power supply
(1) I = input, O = output
GUID-C5361A4D-9FD0-4215-B1DC-8D9E3CF04A8A-low.svgFigure 5-3 OPA2992-Q1 D and DGK Package,
8-Pin SOIC and VSSOP
(Top View)
Table 5-2 Pin Functions: OPA2992-Q1
PIN TYPE(1) DESCRIPTION
NAME NO.
IN1+ 3 I Noninverting input, channel 1
IN1– 2 I Inverting input, channel 1
IN2+ 5 I Noninverting input, channel 2
IN2– 6 I Inverting input, channel 2
OUT1 1 O Output, channel 1
OUT2 7 O Output, channel 2
V+ 8 — Positive (highest) power supply
V– 4 — Negative (lowest) power supply
(1) I = input, O = output
GUID-4B29469F-6C0D-41DF-AE80-410A4E71143C-low.svgFigure 5-4 OPA4992-Q1 D and PW Package,
14-Pin SOIC and TSSOP
(Top View)
Table 5-3 Pin Functions: OPA4992-Q1
PIN TYPE(1) DESCRIPTION
NAME NO.
IN1+ 3 I Noninverting input, channel 1
IN1– 2 I Inverting input, channel 1
IN2+ 5 I Noninverting input, channel 2
IN2– 6 I Inverting input, channel 2
IN3+ 10 I Noninverting input, channel 3
IN3– 9 I Inverting input, channel 3
IN4+ 12 I Noninverting input, channel 4
IN4– 13 I Inverting input, channel 4
OUT1 1 O Output, channel 1
OUT2 7 O Output, channel 2
OUT3 8 O Output, channel 3
OUT4 14 O Output, channel 4
V+ 4 — Positive (highest) power supply
V– 11 — Negative (lowest) power supply
(1) I = input, O = output