SBOSA13A May   2022  – August 2022 OPA3S2859

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Programmable Gain
      2. 8.3.2 Slew Rate
      3. 8.3.3 Input and ESD Protection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Split-Supply and Single-Supply Operation
      2. 8.4.2 Power-Down Mode
      3. 8.4.3 Gain Select Mode (SEL)
      4. 8.4.4 Latch Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Examples
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

VS+ = 5 V, VS- = 0 V, RL = 200 Ω, output load is referenced to midsupply, input common-mode biased at midsupply, and TA ≈ +25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
AC PERFORMANCE
SSBW Small-signal transimpedance bandwidth(1) VOUT = 100 mVPP, Gain = 1 kΩ, CIN= 4 pF 130 MHz
VOUT = 100 mVPP, Gain = 10 kΩ,  CIN = 4 pF 40 MHz
VOUT = 100 mVPP, Gain = 100kΩ, Cin = 4 pF 14 MHz
GBWP Gain-bandwidth product 900 MHz
Slew rate (10% - 90%) VOUT = 2-V step 350 V/µs
en Input-referred voltage noise f = 1 MHz 2.2 nV/√Hz
ZOUT Closed-loop output impedance f = 1 MHz 0.02 Ω
DC PERFORMANCE
AOL Open-loop voltage gain f = DC 70 76 dB
VOS Input offset voltage TA = 25 °C –8 ±0.9 8 mV
ΔVOS/ΔT Input offset voltage drift TA = -40°C to +125°C –2 µV/°C
IBN, IBI Input bias current(2) –50 50 pA
IBOS Input offset current(2) -50 50 pA
CMRR Common-mode rejection ratio VCM =  ±0.5 V (from midsupply) 67 78 dB
INPUTS
CIN+ Non-inverting input capacitance 1.4 pF
CIN- Inverting input capacitance (3) 3 pF
VIH Common-mode input range (high) CMRR > 64 dB 3.4 3.6 V
VIH Common-mode input range (high) CMRR > 64 dB , VS+ = 3.3 V 1.7 1.9 V
VIL Common-mode input range (low) CMRR > 64 dB  0 0.4 V
VIL Common-mode input range (low) CMRR > 64 dB , VS+ = 3.3 V 0 0.4 V
OUTPUTS
VOH Output voltage (high) TA = 25 °C 3.95 4.1 V
VOH Output voltage (high) VS+ = 3.3 V, TA = 25 °C 2.3 2.4 V
VOL Output voltage(low) TA = 25 °C 1.1 1.2 V
VOL Output voltage(low) VS+ = 3.3 V, TA = 25 °C 1.05 1.15 V
IO_LIN Linear output drive (source and sink) RL = 10 Ω, AOL > 52 dB 65 74 mA
CHANNEL-TO-CHANNEL MATCHING
Crosstalk (output-referred) f = 1 MHz, Gain = 100 kΩ, VOUT = 100 mVPP -70 dB
Offset voltage mismatch ±1 mV
Offset current mismatch -20 20 pA
POWER SUPPLY
IQ Quiescent current (both channels)   VS+ = 5 V 44 53 mA
VS+ = 5 V, TA = +125°C 51 mA
VS+ = 5 V, TA = -40°C 39 mA
PSRR+ Power Supply Rejection Ratio f = DC 74 85 dB
PSRR- Power Supply Rejection Ratio f = DC 68 72 dB
POWER DOWN
Disable voltage threshold Voltage referenced to VS+, amplifier OFF below this voltage VS+ - 1.5 VS+ - 1.3 V
Enable voltage threshold Voltage referenced to VS+, amplifier ON above this voltage VS+ - 1.2 VS+ - 0.8 V
Power-down quiescent current 75 140 µA
PD bias current VPD = VS- or VS+ 6 µA
PD bias current VPD at switching threshold 160 µA
Turnon time delay Time to VOUT = 90% of final value 90 ns
Turnoff time delay Time to VOUT = 10% of final value 330 ns
(1) CIN = Photodiode capacitance + PCB capacitance. Photodiode capacitance is 3.3 pF and estimated PCB capacitance is 0.7 pF. 
(2) Leakage currents from switches are not included in this measurement.
(3) CIN- refers to the capacitance at the inverting input of the amplifier. CIN- = CIN-(CM) + CDIFF + Switch capacitance on the amplifier inverting pin (ON capacitance of the closed switch + OFF capacitance for open switches).