SBOS962F April   2020  – March 2023 OPA205 , OPA2205 , OPA4205

PRODMIX  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information: OPA205
    5. 6.5 Thermal Information: OPA2205
    6. 6.6 Thermal Information: OPA4205
    7. 6.7 Electrical Characteristics: VS = ±5 V
    8. 6.8 Electrical Characteristics: VS = ±15 V
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Typical Specifications and Distributions
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Offset Trimming
      2. 8.3.2 Lower Input Bias With Super-Beta Inputs
      3. 8.3.3 Overload Power Limiter
      4. 8.3.4 EMI Rejection
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 High-Precision Signal-Chain Input Buffer
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Discrete, Two-Op-Amp Instrumentation Amplifier
      3. 9.2.3 Second-Order Low-Pass Filter
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
        1. 10.1.1.1 PSpice® for TI
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

GUID-F1943E80-BC49-43D4-B229-FE85B6E056E6-low.gifFigure 5-1 OPA205 D Package, 8-Pin SOIC (Top View)
Table 5-1 Pin Functions: OPA205
PIN TYPE DESCRIPTION
NAME NO.
+IN 3 Input Noninverting input
–IN 2 Input Inverting input
NC 1, 5, 8 — No internal connection (can be left floating)
OUT 6 Output Output
V+ 7 — Positive (highest) power supply
V– 4 — Negative (lowest) power supply
GUID-CD30933B-FDA3-4D18-BF91-4064782A917F-low.gif Figure 5-2 OPA2205 DGK Package, 8-Pin VSSOP and D Package, 8-pin SOIC (Top View)
Table 5-2 Pin Functions: OPA2205
PIN TYPE DESCRIPTION
NAME NO.
+IN A 3 Input Noninverting input, channel A
–IN A 2 Input Inverting input, channel A
+IN B 5 Input Noninverting input, channel B
–IN B 6 Input Inverting input, channel B
OUT A 1 Output Output, channel A
OUT B 7 Output Output, channel B
V+ 8 — Positive (highest) power supply
V– 4 — Negative (lowest) power supply
GUID-E4345B66-106B-4662-8A41-57CE2F2BD88F-low.gif Figure 5-3 OPA4205 PW Package, 14-Pin TSSOP and D Package, 14-Pin SOIC (Top View)
Pin Functions: OPA4205
PIN TYPE DESCRIPTION
NAME NO.
+IN A 3 Input Noninverting input, channel A
+IN B 5 Input Noninverting input, channel B
+IN C 10 Input Noninverting input, channel C
+IN D 12 Input Noninverting input, channel D
–IN A 2 Input Inverting input, channel A
–IN B 6 Input Inverting input, channel B
–IN C 9 Input Inverting input, channel C
–IN D 13 Input Inverting input, channel D
OUT A 1 Output Output, channel A
OUT B 7 Output Output, channel B
OUT C 8 Output Output, channel C
OUT D 14 Output Output, channel D
V+ 4 — Positive (highest) power supply
V– 11 — Negative (lowest) power supply