SBOS376I November   2006  – July 2016 OPA827

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Operating Voltage
      2. 7.3.2 Noise Performance
      3. 7.3.3 Basic Noise Calculations
      4. 7.3.4 Total Harmonic Distortion Measurements
      5. 7.3.5 Capacitive Load and Stability
      6. 7.3.6 Phase-Reversal Protection
      7. 7.3.7 Transimpedance Amplifier
        1. 7.3.7.1 Key Transimpedance Points
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 System Examples
      1. 8.3.1 OPA827 Used as an I/V Converter
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resource
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Supply voltage, VS = (V+) – (V–) 40 V
Input voltage(2) (V–) – 0.5 (V+) + 0.5 V
Input current(2) ±10 mA
Differential input voltage ±VS V
Output short-circuit(3) Continuous
Operating temperature, TA –55 150 °C
Junction temperature, TJ 150 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5 V beyond the supply rails must be current-limited to 10 mA or less.
(3) Short-circuit to VS/2 (ground in symmetrical dual-supply setups).

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±4000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VS Supply voltage ±4 ±18 V
TA Specified temperature –40 125 °C

6.4 Thermal Information

THERMAL METRIC(1) OPA827 UNIT
D (SOIC) DGK (VSSOP)
8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 160 180 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 75 55 °C/W
RθJB Junction-to-board thermal resistance 60 130 °C/W
ψJT Junction-to-top characterization parameter 9 — °C/W
ψJB Junction-to-board characterization parameter 50 120 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance — — °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

at VS = ±4 V to ±18 V, TA = 25°C, RL = 10 kΩ connected to midsupply, and VCM = VOUT = midsupply (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE
VOS Input offset voltage VS = ±15 V, VCM = 0 V 75 150 µV
dVOS/dT Input offset voltage drift TA = –40°C to 125°C 0.1 2 µV/°C
PSRR Input offset voltage vs power supply 0.2 1 µV/V
TA = –40°C to 125°C 3
INPUT BIAS CURRENT
IB Input bias current ±3 ±10 pA
TA = –40°C to 85°C ±500 pA
TA = –40°C to 125°C ±5 nA
IOS Input Offset Current ±3 ±10 pA
NOISE
en Input Voltage Noise: f = 0.1 Hz to 10 Hz, VS = ±18 V, VCM = 0 V 250 nVPP
Input Voltage Noise Density f = 1 kHz, VS = ±18 V, VCM = 0 V 4 nV/√Hz
f = 10 kHz, VS = ±18 V, VCM = 0 V 3.8
in Input current noise density f = 1 kHz, VS = ±18 V, VCM = 0 V 2.2 fA/√Hz
INPUT VOLTAGE RANGE
VCM Common-mode voltage range (V–) + 3 (V+) – 3 V
CMRR Common-mode rejection ratio (V−) + 3 V ≤ VCM ≤ (V+) − 3 V, VS < 10 V 104 114 dB
(V−) + 3 V ≤ VCM ≤ (V+) − 3 V, VS ≥ 10 V 114 126
(V−) + 3 V ≤ VCM ≤ (V+) − 3 V, VS < 10 V
TA = –40°C to 125°C		 100
(V−) + 3 V ≤ VCM ≤ (V+) − 3 V, VS ≥ 10 V
TA = –40°C to 125°C		 110
INPUT IMPEDANCE
Differential 1013 ∥ 9 Ω ∥ pF
Common-mode 1013  ∥ 9 Ω ∥ pF
OPEN-LOOP GAIN
AOL Open-loop voltage gain (V–) + 3 V ≤ VO ≤ (V+) – 3 V, RL = 1 kΩ 120 126 dB
(V–) + 3 V ≤ VO ≤ (V+) – 3 V, RL = 1 kΩ
TA = –40°C to 125°C		 114
FREQUENCY RESPONSE
GBW Gain-bandwidth product G = +1 22 MHz
SR Slew rate G = –1 20 28 V/µs
tS Settling time ±0.01%, 10-V step, G = –1, CL = 100 pF 550 ns
0.00075% (16-bit), 10-V step, G = –1,
CL = 100 pF		 850 ns
Overload recovery time Gain = –10 150 ns
THD+N Total Harmonic Distortion + Noise G = +1, f = 1 kHz 0.00004%
VO = 3 VRMS, RL = 600 Ω –128 dB
OUTPUT
Voltage output swing RL = 1 kΩ, AOL > 120 dB (V–) + 3 (V+) – 3 V
RL = 1 kΩ, AOL > 114 dB
TA = –40°C to 125°C		 (V–) + 3 (V+) – 3
IOUT Output current |VS – VOUT| < 3 V 30 mA
ISC Short-circuit current ±55 ±65 mA
CLOAD Capacitive load drive See Typical Characteristics
ZO Open-loop output impedance See Typical Characteristics
POWER SUPPLY
VS Specified voltage ±4 ±18 V
IQ Quiescent current
(per amplifier)		 IOUT = 0A 4.8 5.2 mA
TA = –40°C to 125°C 6

6.6 Typical Characteristics

At TA = 25°C, VS = ±18 V, RL = 10 kΩ connected to midsupply, and VCM = VOUT = midsupply, unless otherwise noted.
OPA827 tc_v_dens-frq_bos376.gif
Figure 1. Input Voltage Noise Density vs Frequency
OPA827 tc_thdn-frq_bos376.png
Figure 3. Total Harmonic Distortion + Noise Ratio
vs Frequency
OPA827 tc_noise_bos376.gif
Figure 5. 0.1-Hz to 10-Hz Noise
OPA827 tc_histogram_bos376.png
Figure 7. Offset Voltage Drift Production Distribution
OPA827 tc_vos-vcm_36v_bos376.gif
Figure 9. Offset Voltage vs Common-Mode Voltage
OPA827 tc_vos-temp_bos376.gif
Figure 11. Offset Voltage vs Temperature
OPA827 tc_ib-vcm_bos376.gif
Figure 13. Input Bias Current vs Common-Mode Voltage
OPA827 tc_iq-time_bos376.gif
Figure 15. Normalized Quiescent Current vs Time
OPA827 tc_iq-supply_bos376.gif
Figure 17. Quiescent Current vs Supply Voltage
OPA827 tc_ovs-oc_bos376.gif
Figure 19. Output Voltage Swing vs Output Current
OPA827 tc_cmrr-freq_bos376.gif
Figure 21. Common-Mode Rejection Ratio vs Frequency
OPA827 tc_cmrr-temp_bos376.gif
Figure 23. Common-Mode Rejection Ratio vs Temperature
OPA827 tc_close_gain-freq_bos376.gif
Figure 25. Closed-Loop Gain vs Frequency
OPA827 tc_open-imped-freq_bos376.gif
Figure 27. Open-Loop Output Impedance vs Frequency
OPA827 tc_no_phase_bos376.gif
Figure 29. No Phase Reversal
OPA827 tc_neg_recov_bos376.gif
Figure 31. Negative Overload Recovery
OPA827 tc_sm_step_100pf_n1_bos376.gif
Figure 33. Small-Signal Step Response
OPA827 tc_lg_step_n1_bos376.gif
Figure 35. Large-Signal Step Response
OPA827 tc_lg_pos_10_bos376.gif
10 VPP, CL = 10 pF
Figure 37. Large-Signal Positive Settling Time
OPA827 tc_lg_neg_10_bos376.gif
10 VPP, CL = 10 pF
Figure 39. Large-Signal Negative Settling Time
OPA827 tc_inputvn-bw_bos376.gif
Figure 2. Integrated Input Voltage Noise vs Bandwidth
OPA827 tc_thdn-amp_bos376.png
Figure 4. Total Harmonic Distortion + Noise Ratio
vs Amplitude
OPA827 tc_histo_vos_bos376.gif
Figure 6. Offset Voltage Production Distribution
OPA827 tc_vos-vcm_bos376.gif
Figure 8. Offset Voltage vs Common-Mode Voltage
OPA827 tc_vos_warm_bos376.gif
Figure 10. VOS Warmup
OPA827 tc_ib-supply_bos376.png
Figure 12. Input Bias Current and Offset Current
vs Supply Voltage
OPA827 tc_ib-temp_bos376.png
Figure 14. Input Bias Current vs Temperature
OPA827 tc_qc-v-temp_bos376.gif
Figure 16. Quiescent Current vs Temperature
OPA827 tc_averageclaw_bos376.gif
Figure 18. Output Voltage Swing vs Output Current
OPA827 tc_psrr-freq_bos376.gif
Figure 20. Power-Supply Rejection Ratio vs Frequency
OPA827 tc_psrr-tmp_bos376.gif
Figure 22. Power-Supply Rejection Ratio vs Temperature
OPA827 tc_gain-freq_bos376.gif
Figure 24. Open-Loop Gain and Phase vs Frequency
OPA827 tc_aol_1k-tmp_bos376.gif
Figure 26. Open-Loop Gain vs Temperature
OPA827 tc_ss-capload_bos376.gif
Figure 28. Small-Signal Overshoot vs Capacitive Load
OPA827 tc_pos_recov_bos376.gif
Figure 30. Positive Overload Recovery
OPA827 tc_sm_step_10pf_p1_bos376.gif
Figure 32. Small-Signal Step Response
OPA827 tc_lg_step_p1_bos376.gif
Figure 34. Large-Signal Step Response
OPA827 tc_lg_pos_100_bos376.gif
10 VPP, CL = 100 pF
Figure 36. Large-Signal Positive Settling Time
OPA827 tc_lg_neg_100_bos376.gif
10 VPP, CL = 100 pF
Figure 38. Large-Signal Negative Settling Time
OPA827 tc_isc-temp_bos376.gif
Figure 40. Short-Circuit Current vs Temperature