SLOS713J January   2011  – March 2021 OPA2835 , OPA835

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparision Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information: OPA835
    5. 7.5 Thermal Information: OPA2835
    6. 7.6 Electrical Characteristics: VS = 2.7 V
    7. 7.7 Electrical Characteristics: VS = 5 V
    8. 7.8 Typical Characteristics: VS = 2.7 V
    9. 7.9 Typical Characteristics: VS = 5 V
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Common-Mode Voltage Range
      2. 8.3.2 Output Voltage Range
      3. 8.3.3 Power-Down Operation
      4. 8.3.4 Low-Power Applications and the Effects of Resistor Values on Bandwidth
      5. 8.3.5 Driving Capacitive Loads
    4. 8.4 Device Functional Modes
      1. 8.4.1 Split-Supply Operation (±1.25 V to ±2.75 V)
      2. 8.4.2 Single-Supply Operation (2.5 V to 5.5 V)
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1  Noninverting Amplifier
      2. 9.1.2  Inverting Amplifier
      3. 9.1.3  Instrumentation Amplifier
      4. 9.1.4  Attenuators
      5. 9.1.5  Single-Ended to Differential Amplifier
      6. 9.1.6  Differential to Single-Ended Amplifier
      7. 9.1.7  Differential-to-Differential Amplifier
      8. 9.1.8  Gain Setting With OPA835 RUN Integrated Resistors
      9. 9.1.9  Pulse Application With Single-Supply
      10. 9.1.10 ADC Driver Performance
    2. 9.2 Typical Application
      1. 9.2.1 Audio Frequency Performance
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Active Filters
        1. 9.2.2.1 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Related Links
    4. 12.4 Receiving Notification of Documentation Updates
    5. 12.5 Support Resources
    6. 12.6 Trademarks
    7. 12.7 Electrostatic Discharge Caution
    8. 12.8 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Pin Configuration and Functions

GUID-540BCBF2-DB41-46E3-9E08-F07AF0C72EAB-low.gifFigure 6-1 OPA835: DBV Package6-Pin SOT-23Top View
GUID-E13D69B6-08BB-472D-AA69-2A67D3E8C9C7-low.gifFigure 6-3 OPA2835: DGS Package10-Pin VSSOPTop View
GUID-DD412F80-E257-40C0-8957-E8A74A7AC68C-low.gifFigure 6-5 OPA835: RUN Package10-Pin QFNTop View
GUID-A50F5ADE-F0CE-4D8A-80A4-8ADF74E29FA6-low.gifFigure 6-2 OPA2835: D Package8-Pin SOICTop View
GUID-3CA8CA86-C912-49CB-84B6-423ECF0358AC-low.gifFigure 6-4 OPA2835: RMC and RUN Packages10-Pin UQFN and 10-Pin QFNTop View
Table 6-1 Pin Functions
PIN I/O DESCRIPTION
NAME OPA835 OPA2835
SOT-23 QFN SOIC VSSOP QFN,
UQFN
FB1 — 9 — — — I/O Connection to top of 2.4-kΩ internal gain-setting resistors
FB2 8 I/O Connection to junction of 1.8-kΩ and 2.4-kΩ internal gain-setting resistors
FB3 7 I/O Connection to junction of 600-Ω and 1.8-kΩ internal gain-setting resistors
FB4 6 I/O Connection to bottom of 600-Ω internal gain-setting resistors
PD 5 4 I Amplifier Power Down, low = low-power mode,
high = normal operation (PIN MUST BE DRIVEN)
PD1 — — 5 4 I Amplifier 1 Power Down, low = low-power mode,
high = normal operation (PIN MUST BE DRIVEN)
PD2 6 6 I Amplifier 2 Power Down, low = low-power mode,
high = normal operation (PIN MUST BE DRIVEN)
VIN+ 3 3 — — I Amplifier noninverting input
VIN– 4 2 I Amplifier inverting input
VIN1+ — — 3 3 3 I Amplifier 1 noninverting input
VIN1– 2 2 2 I Amplifier 1 inverting input
VIN2+ 5 7 7 I Amplifier 2 noninverting input
VIN2– 6 8 8 I Amplifier 2 inverting input
VOUT 1 1 — — — O Amplifier output
VOUT1 — — 1 1 1 O Amplifier 1 output
VOUT2 7 9 9 O Amplifier 2 output
VS+ 6 10 8 10 10 POW Positive power supply input
VS– 2 5 4 4 5 POW Negative power supply input