SBOSA77A March   2023  – April 2024 OPA928

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics: 4.5V ≤ VS < 8V
    6. 5.6 Electrical Characteristics: 8V ≤ VS ≤ 16V
    7. 5.7 Electrical Characteristics: 16V < VS ≤ 36V
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Guard Buffer
      2. 6.3.2 Input Protection
      3. 6.3.3 Thermal Protection
      4. 6.3.4 Capacitive Load and Stability
      5. 6.3.5 EMI Rejection
      6. 6.3.6 Common-Mode Voltage Range
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Contamination Considerations
      2. 7.1.2 Guarding Considerations
      3. 7.1.3 Single-Supply Considerations
      4. 7.1.4 Humidity Considerations
      5. 7.1.5 Dielectric Relaxation
      6. 7.1.6 Shielding
    2. 7.2 Typical Applications
      1. 7.2.1 High-Impedance Amplifier
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curve
      2. 7.2.2 Transimpedance Amplifier
        1. 7.2.2.1 Design Requirements
        2. 7.2.2.2 Detailed Design Procedure
          1. 7.2.2.2.1 Input Bias
          2. 7.2.2.2.2 Offset Voltage
          3. 7.2.2.2.3 Stability
          4. 7.2.2.2.4 Noise
      3. 7.2.3 Improved Diode Limiter
      4. 7.2.4 Instrumentation Amplifier
    3. 7.3 Power-Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Examples
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 PSpice® for TI
        2. 8.1.1.2 TINA-TI™ Simulation Software (Free Download)
        3. 8.1.1.3 TI Reference Designs
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.5 Electrical Characteristics: 4.5V ≤ VS < 8V

at TA = 25°C, 4.5V ≤ VS < 8V, VGRD = VCM = (V+) – 3V, VOUT = VS / 2, and RL = 10kΩ connected to VS / 2 (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT BIAS CURRENT
IB Input bias current RH < 50%(1) ±1 ±20 fA
TA = –40°C to +85°C ±20
IOS Input offset current RH < 50% (1)(2) ±1 ±20 fA
TA = –40°C to +85°C ±20
OFFSET VOLTAGE
VOS Input offset voltage ±5 ±25 µV
TA = –40°C to +125°C ±20 ±105
dVOS/dT Input offset voltage drift TA = –40°C to +125°C   ±0.1 ±0.8 µV/°C
PSRR Power-supply rejection ratio 4.5V < VS < 36V,
VCM = VS / 2 – 0.75V		 TA = –40°C to +125°C ±0.3 ±1.0 µV/V
NOISE
Input voltage noise (V–) – 0.1V < VCM < (V+) – 3V f = 0.1Hz to 10Hz 1.4 µVPP
en Input voltage noise density (V–) – 0.1V < VCM < (V+) – 3V f = 100Hz 18 nV/√Hz
f = 1kHz 15
in Input current noise density f = 0.1Hz 0.07 fA/√Hz
INPUT VOLTAGE
VCM Common-mode voltage (V–) – 0.1 (V+) + 0.1 V
CMRR Common-mode rejection ratio (V–) – 0.1V < VCM < (V+) – 3V 96 120 dB
TA = –40°C to +125°C 90 104
(V+) – 3V < VCM < (V+) + 0.1V See Typical Characteristics
INPUT IMPEDANCE
ZID Differential 750 || 3 GΩ || pF
ZIC Common-mode 1000 || 6 TΩ || pF
OPEN-LOOP GAIN
AOL Open-loop voltage gain (V–) + 0.6V < VO < (V+) – 0.6V,
RL = 2kΩ		 110 120 dB
TA = –40°C to +125°C 100 114
(V–) + 0.3V < VO < (V+) – 0.3V,
RL = 10kΩ		 110 126
TA = –40°C to +125°C 106 120
FREQUENCY RESPONSE
GBW Unity gain bandwidth 2.5 MHz
SR Slew rate Gain = 1, 1V step Falling 4.5 V/µs
Rising 3.5
ts Settling time Gain = 1, 2V step, CL = 20pF To 0.01%, 2 µs
To 0.001% 7
tOR Overload recovery time VIN × gain = VS From overload to negative rail 0.8 µs
From overload to positive rail 1.2
THD+N Total harmonic distortion + noise Gain = 1, f = 1kHz, VO = 0.5VRMS 0.01%
OUTPUT
VO Voltage output swing from rail No load 5 15 mV
RL = 10kΩ 50 110
RL = 2kΩ 200 500
ISC Short-circuit current ±30 mA
CL Capacitive load drive See Typical Characteristics
ZO Open-loop output impedance f = 1MHz, IO = 0A 800 Ω
POWER SUPPLY
IQ Quiescent current IO = 0A 275 400 µA
TA = –40°C to +125°C 500
TEMPERATURE
Thermal protection 180 °C
Thermal hysteresis 30 °C
INTERNAL GUARD BUFFER
VOSG Guard buffer input offset voltage (V–) + 0.1V < VCM < (V+) – 3V ±8 ±50 µV
TA = –40°C to +125°C ±25 ±150
dVOSG/dT Guard buffer input offset voltage drift TA = –40°C to +125°C ±0.2 ±1.2 µV/°C
VOGB Guard buffer output swing from rail(3) No load 5 15 mV
Guard buffer output impedance IO = 0A 1 kΩ
BWGB Guard buffer bandwidth 4.5 MHz
(1) RH = relative humidity.
(2) Specification established from device population bench system measurements across multiple lots.
(3) The guard pin voltage (VGRD) is limited by the guard buffer output swing unless overdriven by an external source; see also Section 7.1.3.