SCPS145B December 2007 – February 2016 P82B715
The I2C bus capacitance limit of 400 pF restricts practical communication distances to a few meters. One of the advantages of the P82B715 is that it can isolate bus capacitance such that the total loading (devices, connectors, traces and wires) of the new bus or remote I2C nodes are not apparent to other I2C buses (or nodes). This is achieved by using one P82B715 device at each end of a long cable. The pin Lx of one P82B715 device must be connected to Lx of the second P82B715 (similarly for Ly). This allows the total system capacitance load to be around 3000 pF. The P82B715 uses unidirectional analog current amplification to increase the current sink capability of I2C chips to change the 400-pF I2C bus specification limit into a 3-nF bus wiring capacitance limit. That means longer cables or lower-cost general-purpose wiring may be used to connect two separate I2C-based systems, without worrying about the special voltage levels associated with other I2C bus buffers.
Multiple P82B715s can be connected together in a star or multipoint architecture by their Lx/Ly ports, without limit, as long as the total capacitance of the system remains less than about 3000 pF (400 pF or less when referenced to any Sx/Sy connection). In that arrangement, the master and/or slave devices are attached to the Sx/Sy port of each P82B715. In normal use, the power-supply voltages at each end of the low-impedance buffered bus line should be the same. If these differ by a significant amount, noise margin is sacrificed.
Two or more Sx or Sy I/Os can be interconnected and are also fully compatible with bus buffers that use voltage-level offsets (such as the TCA9517) because it duplicates and transmits the offset voltage.
The I2C pins (Sx and Sy) are designed to interface with a normal I2C bus. The maximum I2C bus supply voltage is 12 V. The Sx and Sy pins contain identical circuitry and can be used interchangeably as SCL or SDA.
The Lx and Ly pins are designed to interface with the high capacitance bus. This port of the device features circuitry to assist in sinking large amounts of currents required to operate a large capacitance bus at high speeds. More on this circuitry can be found in Lx/Ly Buffered Bus Circuitry.
On the special low-impedance or buffered-line side, the corresponding output becomes the LDA data line or LCL clock line. The P82B715 provides current amplification from its I2C bus to its low impedance or buffered bus. Whenever current is flowing out of Sx into an I2C chip driving the I2C bus low, its amplifier sinks ten times that current into Lx, to drive the buffered bus low (see Figure 3). To minimize interference and ensure stability, the current rise and fall times of the Lx drive amplifier are internally controlled. The P82B715 does not amplify signal currents flowing into Sx on the I2C bus driven by currents flowing out of Lx on the buffered side. A buffered bus logic low signal at Lx passes through the internal 30-Ω resistor to drive the I2C bus low. This signal current amplification, dependent on its direction, preserves the multi-master bidirectional open-collector/open-drain characteristic of any connected I2C bus lines and the new low-impedance bus. Bus logic-signal voltage levels are clamped at (VCC + 0.7 V) but, otherwise, are independent of the supply voltage, VCC.
The P82B715 has two modes when powered, which depend on the state of the I2C bus.
When the I2C bus is idle and high, little or no current flows through the device. In this case, the Lx/Ly buffer is not turned on.
When a device connected to the Sx / Sy side of the device is transmitting a 0, a large amount of current will flow through the P82B715, which activates the internal pulldown to assist with the large capacitance.