SCPS232B March   2012  – March 2016 PCA9515B

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Two-Channel Bidirectional Buffer
      2. 8.3.2 Bidirectional Voltage-Level Translation
      3. 8.3.3 Active-High Enable Input
    4. 8.4 Device Functional Modes
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Detailed Description

8.1 Overview

The PCA9515B is a BiCMOS dual bidirectional buffer integrated circuit intended for I2C bus and SMBus applications. The device contains two identical bidirectional open-drain buffer circuits that enables I2C and similar bus systems to be extended without degrading system performance. This device enables I2C and similar bus systems to be extended (and add more slaves) without degradation of performance. The dual bidirectional I2C buffer is operational at 2.3 V to 3.6 V VCC.

The PCA9515B buffers both the serial data (SDA) and serial clock (SCL) signals on the I2C bus, while retaining all the operating modes and features of the I2C system. The device allows two buses, of 400-pF bus capacitance, to be connected in an I2C application.

The I2C bus capacitance limit of 400 pF restricts the number of slave devices and bus length. Using the PCA9515B, a system designer can capacitively isolate two halves of a bus, thus accommodating more I2C devices and longer trace lengths.

The PCA9515B has an active-high enable (EN) input with an internal pull-up. This allows users to select when the repeater is active and isolate malfunctioning slaves on power-up reset. States should never be changed during an I2C operation. Disabling during a bus operation will hang the bus and enabling part way through a bus cycle may confuse the I2C parts being enabled. The EN input should only change state when the global bus and the repeater port are in an idle state to prevent system failures.

The PCA9515B can also be used to operate two buses, one at 5 V interface levels and the other at 3.3 V interface levels. The buses may also function at 400-kHz or 100-kHz operating frequency. If the two buses are operating at different frequencies, the 100-kHz bus must be isolated if the operation of the 400-kHz bus is required. If the master is running at 400-kHz, the maximum system operating frequency may be less than 400 kHz because of the delays added by the repeater.

The low level outputs for each internal buffer are approximately 0.5 V; however, the input voltage of each internal buffer must be 70 mV or more below the low level output when the output is driven low internally. This prevents a lockup condition from occurring when the input low condition is released.

Two or more PCA9515B devices cannot be used in series. Since there is no direction pin, different valid low-voltage levels are used to avoid lockup conditions between the input and the output of each repeater. A valid low, applied at the input of a PCA9515B, is propagated as a buffered low with a higher value on the enabled outputs. When this buffered low is applied to another PCA9515B-type device in series, the second device does not recognize it as a valid low and does not propagate it as a buffered low.

The device contains a power-up control circuit that sets an internal latch to prevent the output circuits from becoming active until VCC is at a valid level (VCC = 2.3 V).

As with the standard I2C system, pullup resistors are required to provide the logic high levels on the buffered bus. The PCA9515B has standard open-collector configuration of the I2C bus. The size of the pullup resistors depend on the system; however, each side of the repeater must have a pullup resistor. The device is designed to work with Standard Mode and Fast Mode I2C devices in addition to SMBus devices. Standard Mode I2C devices only specify a 3 mA termination current in a generic I2C system where Standard Mode devices and multiple masters are possible. Under certain conditions, high termination currents can be used.

8.2 Functional Block Diagram

PCA9515B ld_cps232.gif
Figure 4. Logic Diagram (Poisitve Logic)

8.3 Feature Description

8.3.1 Two-Channel Bidirectional Buffer

The PCA9515B is a two-channel bidirectional buffer for open-drain applications like I2C and SMBus.

8.3.2 Bidirectional Voltage-Level Translation

The PCA9515B allows bidirectional voltage-level translation (up-translation and down-translation) between low voltages (down to 2.3 V) and higher voltages (up to 5.5 V).

8.3.3 Active-High Enable Input

The PCA9515B has an active-high enable (EN) input with an internal pull-up to VCC. The enable input needs to be pulled to GND to disable the PCA9515B and isolate the I2C buses. Pulling-up the enable pin or floating the enable pin causes the PCA9515B to turn on and buffer the I2C bus.

8.4 Device Functional Modes

The PCA9515B has an active-high enable (EN) input with an internal pull-up to VCC, which allows the user to select when the repeater is active. This can be used to isolate a badly behaved slave on power-up reset. It should never change state during an I2C operation, because disabling during a bus operation my hang the bus, and enabling part way through the bus cycles could confuse the I2C parts being enabled. The EN input should only change state when the global bus and repeater port are in the idle state to prevent system failures. Table 1 lists the PCA9515B functions.

Table 1. Function Table

INPUT
EN
FUNCTION
L Outputs disabled
H SDA0 = SDA1,
SCL0 = SCL1