SCPS126G September   2006  – March 2021 PCA9538

PRODUCTION DATA  

  1. 1 Features
  2. 2 Description
  3. 3 Revision History
  4. 4 Pin Configuration and Functions
  5. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 I2C Interface Timing Requirements
    7. 5.7 RESET Timing Requirements
    8. 5.8 Switching Characteristics
    9. 5.9 Typical Characteristics
  6. 6 Parameter Measurement Information
  7. 7 Detailed Description
    1. 7.1 Functional Block Diagram
    2. 7.2 Device Functional Modes
      1. 7.2.1 RESET Input
        1. 7.2.1.1 RESET Errata
          1.        System Impact
          2.        System Workaround
      2. 7.2.2 Power-On Reset
      3. 7.2.3 I/O Port
      4. 7.2.4 Interrupt Output ( INT)
        1. 7.2.4.1 Interrupt Errata
          1.        System Impact
          2.        System Workaround
    3. 7.3 Programming
      1. 7.3.1 I2C Interface
    4. 7.4 Register Maps
      1. 7.4.1 Device Address
      2. 7.4.2 Control Register And Command Byte
      3. 7.4.3 Register Descriptions
      4. 7.4.4 Bus Transactions
        1. 7.4.4.1 Writes
        2. 7.4.4.2 Reads
  8. 8 Application Information Disclaimer
    1. 8.1 Application Information Disclaimer
    2. 8.2 Typical Application
      1. 8.2.1 Detailed Design Procedure
        1. 8.2.1.1 Minimizing ICC When I/Os Control Leds
  9. 9 Power Supply Recommendations
    1. 9.1 Power-On Reset Requirements
  10. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.6 I2C Interface Timing Requirements

over operating free-air temperature range (unless otherwise noted) (see Figure 6-1)
MINMAXUNIT
STANDARD MODE
fsclI2C clock frequency0100kHz
tschI2C clock high time4μs
tsclI2C clock low time4.7μs
tspI2C spike time50ns
tsdsI2C serial-data setup time250ns
tsdhI2C serial-data hold time0ns
ticrI2C input rise time1000ns
ticfI2C input fall time300ns
tocfI2C output fall time10-pF to 400-pF bus300ns
tbufI2C bus free time between Stop and Start4.7μs
tstsI2C Start or repeated Start condition setup4.7μs
tsthI2C Start or repeated Start condition hold4μs
tspsI2C Stop condition setup4μs
tvd(data)Valid data timeSCL low to SDA output valid300ns
tvd(ack)Valid data time of ACK conditionACK signal from SCL low to
SDA (out) low		0.33.45μs
CbI2C bus capacitive load400ns
FAST MODE
fsclI2C clock frequency0400kHz
tschI2C clock high time0.6μs
tsclI2C clock low time1.3μs
tspI2C spike time50ns
tsdsI2C serial-data setup time100ns
tsdhI2C serial-data hold time0ns
ticrI2C input rise time20 + 0.1Cb (1)300ns
ticfI2C input fall time20 + 0.1Cb (1)300ns
tocfI2C output fall time10-pF to 400-pF bus20 + 0.1Cb (1)300ns
tbufI2C bus free time between Stop and Start1.3μs
tstsI2C Start or repeated Start condition setup0.6μs
tsthI2C Start or repeated Start condition hold0.6μs
tspsI2C Stop condition setup0.6μs
tvd(data)Valid data timeSCL low to SDA output valid50ns
tvd(ack)Valid data time of ACK conditionACK signal from SCL low to
SDA (out) low		0.10.9μs
CbI2C bus capacitive load400ns
(1) Cb = Total capacitance of one bus in pF