SCPS143G June 2009 – March 2021 PCA9548A
The A0, A1, and A2 pins are hardware selectable to control the slave address of the PCA9548A. These pins may be tied directly to GND or VCC in the application.
If multiple slave channels are activated simultaneously in the application, then the total IOL from SCL/SDA to GND on the master side is the sum of the currents through all pull-up resistors, Rp.
The pass-gate transistors of the PCA9548A are constructed such that the VCC voltage can be used to limit the maximum voltage that is passed from one I2C bus to another.
Figure 9-2 shows the voltage characteristics of the pass-gate transistors (note that the graph was generated using data specified in the Electrical Characteristics section of this data sheet). In order for the PCA9548A to act as a voltage translator, the Vpass voltage must be equal to or lower than the lowest bus voltage. For example, if the main bus is running at 5 V and the downstream buses are 3.3 V and 2.7 V, Vpass must be equal to or below 2.7 V to effectively clamp the downstream bus voltages. As shown in Figure 9-2, Vpass(max) is 2.7 V when the PCA9548A supply voltage is 4 V or lower, so the PCA9548A supply voltage could be set to 3.3 V. Pull-up resistors then can be used to bring the bus voltages to their appropriate levels (see Figure 9-1).