SCPS127F September   2006  – March 2021 PCA9554A

PRODUCTION DATA  

  1. 1 Features
  2. 2 Description
  3. 3 Revision History
  4. 4 Description (Continued)
  5. 5 Pin Configuration And Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Interface Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Functional Block Diagram
    2. 8.2 Device Functional Modes
      1. 8.2.1 Power-On Reset
      2. 8.2.2 I/O Port
      3. 8.2.3 Interrupt Output ( INT)
        1. 8.2.3.1 Interrupt Errata
          1. 8.2.3.1.1 Description
          2. 8.2.3.1.2 System Impact
          3. 8.2.3.1.3 System Workaround
    3. 8.3 Programming
      1. 8.3.1 I2C Interface
      2. 8.3.2 Register Map
        1. 8.3.2.1 Device Address
        2. 8.3.2.2 Control Register And Command Byte
        3. 8.3.2.3 Register Descriptions
        4. 8.3.2.4 Bus Transactions
          1. 8.3.2.4.1 Writes
          2. 8.3.2.4.2 Reads
  9. 9 Application Information Disclaimer
    1. 9.1 Application Information
      1. 9.1.1 Typical Application
        1. 9.1.1.1 Detailed Design Procedure
          1. 9.1.1.1.1 Minimizing ICC When I/Os Control Leds
  10. 10Power Supply Recommendations
    1. 10.1 Power-On Reset Requirements
  11. 11Device and Documentation Support
    1. 11.1 Support Resources
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.2.1 Device Address

Figure 8-6 shows the address byte for the PCA9554A.

GUID-6BADF48D-7A9C-4EFD-9E55-19F6FA13D9C8-low.gifFigure 8-6 Pca9554a Address
Table 8-2 Address Reference
INPUTSI2C BUS SLAVE ADDRESS
A2A1A0
LLL56 (decimal), 38 (hexadecimal)
LLH57 (decimal), 39 (hexadecimal)
LHL58 (decimal), 3A (hexadecimal)
LHH59 (decimal), 3B (hexadecimal)
HLL60 (decimal), 3C (hexadecimal)
HLH61 (decimal), 3D (hexadecimal)
HHL62 (decimal), 3E (hexadecimal)
HHH63 (decimal), 3F (hexadecimal)

The last bit of the slave address defines the operation (read or write) to be performed. When it is high (1), a read is selected. A low (0) selects a write operation.