SLES177B April 2006 – August 2015 PCM1808
Bypass the digital and analog power supply lines to the PCM1808 device to the corresponding ground pins with both 0.1-μF ceramic and 10-μF electrolytic capacitors as close to the pins as possible to maximize the dynamic performance of the ADC.
To maximize the dynamic performance of the PCM1808 device, there are no internal connections to the analog and digital grounds. These grounds should have low impedance to avoid digital noise feedback into the analog ground. They should be connected directly to each other under the PCM1808 device package to reduce potential noise problems.
VINL and VINR are single-ended inputs. These inputs have integrated antialias low-pass filters to remove the high-frequency noise outside the audio band. If the performance of these filters is not adequate for an application, the application requires appropriate external antialiasing filters. An appropriate choice would typically be a passive RC filter in the range of 100 Ω and 0.01 μF to 1 kΩ and 1000 pF.
To ensure low source impedance of the ADC references, the recommended capacitors between VREF and AGND are 0.1-μF ceramic and 10-μF electrolytic. These capacitors should be located as close as possible to the VREF pin to reduce dynamic errors on the ADC references.
The DOUT pin has a large load-drive capability, but if the DOUT line is long, a recommended practice is to locate a buffer near the PCM1808 device and minimize load capacitance to minimize the digital-analog crosstalk and maximize the dynamic performance of the ADC.
The quality of the system clock can influence dynamic performance, as the PCM1808 device operates based on a system clock. Therefore, it may be necessary to consider the system clock duty, jitter, and the time difference between system clock transition and BCK or LRCK transition in slave mode.