SBASAH4A April   2022  – September 2022 PCM1820-Q1 , PCM1821-Q1

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4.     Thermal Information
    5. 7.4 Electrical Characteristics
    6. 7.5 Timing Requirements: TDM, I2S or LJ Interface
    7. 7.6 Switching Characteristics: TDM, I2S or LJ Interface
    8. 7.7 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Hardware Control
      2. 8.3.2 Audio Serial Interfaces
        1. 8.3.2.1 Time Division Multiplexed Audio (TDM) Interface
        2. 8.3.2.2 Inter IC Sound (I2S) Interface
      3. 8.3.3 Phase-Locked Loop (PLL) and Clock Generation
      4. 8.3.4 Input Channel Configurations
      5. 8.3.5 Reference Voltage
      6. 8.3.6 Signal-Chain Processing
        1. 8.3.6.1 Digital High-Pass Filter
        2. 8.3.6.2 Configurable Digital Decimation Filters
          1. 8.3.6.2.1 Linear Phase Filters
            1. 8.3.6.2.1.1 Sampling Rate: 8 kHz or 7.35 kHz
            2. 8.3.6.2.1.2 Sampling Rate: 16 kHz or 14.7 kHz
            3. 8.3.6.2.1.3 Sampling Rate: 24 kHz or 22.05 kHz
            4. 8.3.6.2.1.4 Sampling Rate: 32 kHz or 29.4 kHz
            5. 8.3.6.2.1.5 Sampling Rate: 48 kHz or 44.1 kHz
            6. 8.3.6.2.1.6 Sampling Rate: 96 kHz or 88.2 kHz
            7. 8.3.6.2.1.7 Sampling Rate: 192 kHz or 176.4 kHz
          2. 8.3.6.2.2 Low-Latency Filters
            1. 8.3.6.2.2.1 Sampling Rate: 16 kHz or 14.7 kHz
            2. 8.3.6.2.2.2 Sampling Rate: 24 kHz or 22.05 kHz
            3. 8.3.6.2.2.3 Sampling Rate: 32 kHz or 29.4 kHz
            4. 8.3.6.2.2.4 Sampling Rate: 48 kHz or 44.1 kHz
            5. 8.3.6.2.2.5 Sampling Rate: 96 kHz or 88.2 kHz
      7. 8.3.7 Dynamic Range Enhancer (DRE)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Active Mode
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Overview

The PCM182(0/1)-Q1 is a high-performance, low-power, stereo-channel, audio analog-to-digital converter (ADC) with flexible audio interface control options. This device is intended for applications in automotive head units, display control unit, Active Noise Cancellation and Acoustic Echo Cancellation applications. The high dynamic range of the device enables far-field audio recording with high fidelity. This device integrates a host of features that reduces cost, board space, and power consumption in space-constrained applications. The device features are controlled through hardware by pulling pins high or low with resistors or a controller general-purpose inut/output (GPIO). The PCM182(0/1)-Q1 also supports a power-down and reset function by means of halting the system clock.

The PCM182(0/1)-Q1 consists of the following blocks and features:

  • Stereo-channel, multibit, high-performance delta-sigma (ΔΣ) ADC
  • Differential audio inputs with a 2-VRMS full-scale signal
  • Hardware pin control operation to select the device features
  • Audio bus serial interface master or slave select option
  • Audio bus serial interface format select option
  • Slave mode supports the audio bus serial interface up to 192 kHz sampling
  • Slave mode supports a dynamic range enhancer (DRE) with 123-dB dynamic range for the PCM1820-Q1
  • Slave mode supports decimation filters with linear-phase or low-latency filter selection
  • Master mode operation supported using a system clock of 256 × fS or 512 × fS
  • Power-down function by means of halting the audio clocks
  • Integrated high-pass filter (HPF) that removes the DC component of the input signal
  • Integrated low-jitter phase-locked loop (PLL) supporting a wide range of system clocks
  • Integrated digital and analog voltage regulators to support single-supply, 3.3-V operation