SLAS759B August   2012  – January 2016 PCM5141 , PCM5142


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison
  6. Pin Configuration and Functions
    1. 6.1 Pin Functions
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Timing Requirements: SCK Input
    7. 7.7  Timing Requirements: PCM Audio Data
      1. 7.7.1 Timing Requirements: I2S Master
    8. 7.8  Timing Requirements: XSMT
    9. 7.9  Switching Characteristics
    10. 7.10 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Terminology
      2. 8.3.2 Audio Data Interface
        1. Audio Serial Interface
        2. PCM Audio Data Formats
        3. Zero Data Detect
      3. 8.3.3 XSMT Pin (Soft Mute / Soft Un-Mute)
      4. 8.3.4 Audio Processing
        1. PCM514x Audio Processing Options
          1. Overview
          2. miniDSP Instruction Register
          3. Digital Output
          4. Software
        2. Interpolation Filter
        3. Fixed Audio Processing Flow (Program 5)
          1. Processing Blocks - Detailed Descriptions
          2. Biquad Section
          3. Dynamic Range Compression
          4. Stereo Mixer
          5. Stereo Multiplexer
          6. Mono Mixer
          7. Master Volume Control
          8. Miscellaneous Coefficients
      5. 8.3.5 DAC Outputs
        1. Analog Outputs
        2. Recommended Output Filter for the PCM514x
        3. Choosing Between VREF and VCOM Modes
          1. Voltage Reference and Output Levels
          2. Mode Switching Sequence, from VREF Mode to VCOM Mode
        4. Digital Volume Control
          1. Emergency Ramp-Down
        5. Analog Gain Control
      6. 8.3.6 Reset and System Clock Functions
        1. Clocking Overview
        2. Clock Slave Mode With Master and System Clock (SCK) Input (4 Wire I2S)
        3. Clock Slave Mode With BCK PLL to Generate Internal Clocks (3-Wire PCM)
        4. Clock Generation Using the PLL
        5. PLL Calculation
          1. Examples:
            1. Recommended PLL Settings
        6. Clock Master Mode from Audio Rate Master Clock
        7. Clock Master from a Non-Audio Rate Master Clock
    4. 8.4 Device Functional Modes
      1. 8.4.1 Choosing a Control Mode
        1. Software Control
          1. SPI Interface
            1. Register Read and Write Operation
          2. I2C Interface
            1. Slave Address
            2. Register Address Auto-Increment Mode
            3. Packet Protocol
            4. Write Register
            5. Read Register
            6. Timing Characteristics
      2. 8.4.2 VREF and VCOM Modes
    5. 8.5 Programming
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply Distribution and Requirements
    2. 10.2 Recommended Powerdown Sequence
      1. 10.2.1 XSMT = 0
      2. 10.2.2 Clock Error Detect
      3. 10.2.3 Planned Shutdown
      4. 10.2.4 Unplanned Shutdown
    3. 10.3 External Power Sense Undervoltage Protection Mode
    4. 10.4 Power-On Reset Function
      1. 10.4.1 Power-On Reset, DVDD 3.3-V Supply
      2. 10.4.2 Power-On Reset, DVDD 1.8-V Supply
    5. 10.5 PCM514x Power Modes
      1. 10.5.1 Setting Digital Power Supplies and I/O Voltage Rails
      2. 10.5.2 Power Save Modes
      3. 10.5.3 Power Save Parameter Programming
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Register Maps
    1. 12.1 PCM514x Register Map
      1. 12.1.1 Detailed Register Descriptions
        1. Register Map Summary
        2. Page 0 Registers
        3. Page 1 Registers
        4. Page 44 Registers
        5. Page 253 Registers
      2. 12.1.2 PLL Tables for Software Controlled Devices
      3. 12.1.3 Coefficient Data Formats
      4. 12.1.4 Power Down and Reset Behavior
  13. 13Device and Documentation Support
    1. 13.1 Development Support
    2. 13.2 Documentation Support
    3. 13.3 Related Links
    4. 13.4 Community Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Power Supply Recommendations

10.1 Power Supply Distribution and Requirements

The PCM514x devices are powered through the pins shown in Figure 79.

PCM5141 PCM5142 pcm5xxx_pwrtree.gif Figure 79. Power Distribution Tree Within PCM514x

Table 46. Power Supply Pin Descriptions

AVDD Analog voltage supply; must be 3.3 V. This powers all analog circuitry that the DAC runs on.
DVDD Digital voltage supply. This is used as the I/O voltage control and the input to the onchip LDO.
CPVDD Charge Pump Voltage Supply - must be 3.3 V
LDOO Output from the onchip LDO. Should be used with a 0.1-µF decoupling cap. Can be driven (used as power input) with a 1.8-V supply to bypass the onchip LDO for lower power consumption.
AGND Analog ground
DGND Digital ground

10.2 Recommended Powerdown Sequence

Under certain conditions, the PCM514x devices can exhibit some pops on power down. Pops are caused by a device not having enough time to detect power loss and start the muting process.

The PCM514x devices have two auto-mute functions to mute the device upon power loss (intentional or unintentional).

10.2.1 XSMT = 0

When the XSMT pin is pulled low, the incoming PCM data is attenuated to 0, closely followed by a hard analog mute. This process takes 150 sample times (ts) + 0.2 ms.

Because this mute time is mainly dominated by the sampling frequency, systems sampling at 192 kHz will mute much faster than a 48-kHz system.

10.2.2 Clock Error Detect

When clock error is detected on the incoming data clock, the PCM514x devices switch to an internal oscillator, and continue to the drive the output, while attenuating the data from the last known value. Once this process is complete, the PCM514x outputs are hard muted to ground.

10.2.3 Planned Shutdown

These auto-muting processes can be manipulated by system designs to mute before power loss in the following ways:

  1. Assert XSMT low 150 tS + 0.2 ms before power is removed.
  2. PCM5141 PCM5142 f_pcm51xx_anti-pop_pwrdwn_seq.gif Figure 80. Assert XSMT
  3. Stop I2S clocks (SCK, BCK, LRCK) 3 ms before powerdown as shown in Figure 81.
  4. PCM5141 PCM5142 f_pcm51xx_anti-pop_pwrdwn_seq2.gif Figure 81. Stop I2C Clocks

10.2.4 Unplanned Shutdown

Many systems use a low-noise regulator to provide an AVDD 3.3-V supply for the DAC. The XSMT Pin can take advantage of such a feature to measure the pre-regulated output from the system SMPS to mute the output before the entire SMPS discharges. Figure 82 shows how to configure such a system to use the XSMT pin. The XSMT pin can also be used in parallel with a GPIO pin from the system microcontroller/DSP or power supply.

PCM5141 PCM5142 f_pcm51xx_xsmt_anti_pwrdwnpop.gif Figure 82. Using the XSMT Pin

10.3 External Power Sense Undervoltage Protection Mode


External Power Sense Undervoltage Protection Mode is supported only when
DVDD = 3.3 V.

The XSMT pin can also be used to monitor a system voltage, such as the 24-VDC LCD TV backlight, or 12-VDC system supply using a voltage divider created with two resistors. (See Figure 83.)

  • If the XSMT pin makes a transition from 1 to 0 over 6 ms or more, the device switches into external undervoltage protection mode. This mode uses two trigger levels:
    • When the XSMT pin level reaches 2 V, soft mute process begins.
    • When the XSMT pin level reaches 1.2 V, analog mute engages, regardless of digital audio level, and analog shutdown begins. (DAC and related circuitry powers down).

If XSMT is moved from 1 to 0 in 20 ns or less, then the device will interpret it as a digital controlled request to mute. It will perform a soft mute, then move to standby.

A timing diagram to show this is shown in Figure 84.


The XSMT input pin voltage range is from –0.3 V to DVDD + 0.3 V. The ratio of external resistors must produce a voltage within this input range. Any increase in power supply (such as power supply positive noise or ripple) can pull the XSMT pin higher than DVDD + 0.3 V.

For example, if the PCM514x is monitoring a 12-V input, and dividing the voltage by 4, then the voltage at XSMT during ideal power supply conditions is 3.3 V. A voltage spike higher than 14.4 V causes a voltage greater than 3.6 V (DVDD + 0.3) on the XSMT pin, potentially damaging the device.

Providing the divider is set appropriately, any DC voltage can be monitored.

PCM5141 PCM5142 f_pcm51xx_xsmt_ext_uvp_ckt.gif Figure 83. XSMT in External UVP Mode
PCM5141 PCM5142 f_pcm51xx_td_xsmt_uvp.gif Figure 84. XSMT Timing for Undervoltage Protection

The trigger voltage values for the soft mute and hard mute are shown in Table 47. The range of values will vary from device to device, but typical thresholds are shown. XSMT should be set up to nominally be 3.3 V along with DVDD, but derived from a higher system power supply rail.

Table 47. Distribution of Voltage Thresholds

Soft Mute Threshold Voltage 2 2.2 0.9 × DVDD V
Hard Mute Threshold Voltage 0.1 × DVDD 0.9 1.2 V

10.4 Power-On Reset Function

10.4.1 Power-On Reset, DVDD 3.3-V Supply

The PCM514x includes a power-on reset function, as shown in Figure 85. With VDD > 2.8 V, the power-on reset function is enabled. After the initialization period, the PCM514x is set to its default reset state. Analog output will begin ramping after valid data has been passing through the device for the given group delay given by the digital interpolation filter selected.

PCM5141 PCM5142 pcm512x4x_por_3p3.gif Figure 85. Power-On Reset Timing, DVDD = 3.3 V

10.4.2 Power-On Reset, DVDD 1.8-V Supply

The PCM514x includes a power-on reset function, as shown in Figure 86. With AVDD greater than approximately 2.8 V, CPVDD greater than approximately 2.8 V, and DVDD greater than approximately 1.5 V, the power-on reset function is enabled. After the initialization period, the PCM514x is set to its default reset state.

PCM5141 PCM5142 pcm512x4x_por_1p8.gif Figure 86. Power-On Reset Timing, DVDD = 1.8 V

10.5 PCM514x Power Modes

10.5.1 Setting Digital Power Supplies and I/O Voltage Rails

The internal digital core of the PCM514x devices run from a 1.8-V supply. This can be generated by the internal LDO, or by an external 1.8-V supply.

DVDD is used to set the I/O voltage, and to be used as the input to the onchip LDO that creates the 1.8 V required by the digital core.

For systems that require 3.3-V I/O support, but lower power consumption, DVDD should be connected to 3.3 V and LDOO can be connected to an external 1.8-V source. Doing so will disable the onchip LDO.

When setting I/O voltage to be 1.8 V, both DVDD and LDOO must be provided with an external 1.8-V supply.

10.5.2 Power Save Modes

The PCM514x devices offer two power-save modes: standby and power-down.

When a clock error (SCK, BCK, and LRCK) or clock halt is detected, the PCM514x device automatically enters standby mode. The DAC and line driver are also powered down.

When BCK and LRCK remain at a low level for more than 1 second, the PCM514x device automatically enters powerdown mode. Power-down mode disables the negative charge pump and bias/reference circuit, in addition to those disabled in standby mode.

When expected audio clocks (SCK, BCK, LRCK) are applied to the PCM514x device, or if BCK and LRCK start correctly while SCK remains at ground level for 16 successive LRCK periods, the device starts its powerup sequence automatically.

10.5.3 Power Save Parameter Programming

Table 48. Power Save Registers

Page 0, Register 2, D(4) Software standby mode command
Page 0, Register 2, D(0) Software power-down command
Page 0, Register 2, D(4) and D(0) Software power-up sequence command (required after software standby or power-down)
Page 0, Register 44, D(2:0) Detection time of BCK and LRCK halt