SLASE63 November   2014 PCM5252

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
    1. 6.1 Control Mode Effect On Pin Assignments
    2. 6.2 Pin Assignments
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Switching Characteristics
    7. 7.7  Timing Requirements: SCK Input
    8. 7.8  Timing Requirements: PCM Audio Data
    9. 7.9  Timing Requirements: I2S Master, See
    10. 7.10 Timing Requirements: XSMT
    11. 7.11 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Terminology
      2. 8.3.2 Audio Data Interface
        1. 8.3.2.1 Audio Serial Interface
        2. 8.3.2.2 PCM Audio Data Formats
        3. 8.3.2.3 Zero Data Detect
      3. 8.3.3 XSMT Pin (Soft Mute / Soft Un-Mute)
      4. 8.3.4 Audio Processing
        1. 8.3.4.1  PCM5252 Audio Processing Options
          1. 8.3.4.1.1 Overview
          2. 8.3.4.1.2 miniDSP Instruction Register
          3. 8.3.4.1.3 Digital Output
          4. 8.3.4.1.4 Software
        2. 8.3.4.2  Interpolation Filter
        3. 8.3.4.3  Overview
        4. 8.3.4.4  Smart SOA
        5. 8.3.4.5  Smart BASS
        6. 8.3.4.6  Smart Protection
        7. 8.3.4.7  Implementing a Real World Design
        8. 8.3.4.8  Digital Output
        9. 8.3.4.9  Software
        10. 8.3.4.10 Process Flow
      5. 8.3.5 DAC and Differential Analog Outputs
        1. 8.3.5.1 Analog Outputs
        2. 8.3.5.2 Choosing Between VREF and VCOM Modes
          1. 8.3.5.2.1 Voltage Reference and Output Levels
          2. 8.3.5.2.2 Mode Switching Sequence, from VREF Mode to VCOM Mode
        3. 8.3.5.3 Digital Volume Control
          1. 8.3.5.3.1 Emergency Ramp-Down
        4. 8.3.5.4 Analog Gain Control
      6. 8.3.6 Reset and System Clock Functions
        1. 8.3.6.1 Clocking Overview
        2. 8.3.6.2 Clock Slave Mode With Master and System Clock (SCK) Input (4 Wire I2S)
        3. 8.3.6.3 Clock Slave Mode With BCK PLL to Generate Internal Clocks (3-Wire PCM)
        4. 8.3.6.4 Clock Generation Using the PLL
        5. 8.3.6.5 PLL Calculation
          1. 8.3.6.5.1 Examples:
            1. 8.3.6.5.1.1 Recommended PLL Settings
        6. 8.3.6.6 Clock Master Mode from Audio Rate Master Clock
        7. 8.3.6.7 Clock Master from a Non-Audio Rate Master Clock
    4. 8.4 Device Functional Modes
      1. 8.4.1 Choosing a Control Mode
        1. 8.4.1.1 Software Control
          1. 8.4.1.1.1 SPI Interface
            1. 8.4.1.1.1.1 Register Read and Write Operation
          2. 8.4.1.1.2 I2C Interface
            1. 8.4.1.1.2.1 Slave Address
            2. 8.4.1.1.2.2 Register Address Auto-Increment Mode
            3. 8.4.1.1.2.3 Packet Protocol
            4. 8.4.1.1.2.4 Write Register
            5. 8.4.1.1.2.5 Read Register
            6. 8.4.1.1.2.6 Timing Characteristics
      2. 8.4.2 VREF and VCOM Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 High Fidelity Smartphone Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Initialization Script
        3. 9.2.1.3 Application Performance Plot
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply Distribution and Requirements
    2. 10.2 Recommended Powerdown Sequence
      1. 10.2.1 XSMT = 0
      2. 10.2.2 Clock Error Detect
      3. 10.2.3 Planned Shutdown
      4. 10.2.4 Unplanned Shutdown
    3. 10.3 External Power Sense Undervoltage Protection Mode
    4. 10.4 Power-On Reset Function
      1. 10.4.1 Power-On Reset, DVDD 3.3-V Supply
      2. 10.4.2 Power-On Reset, DVDD 1.8-V Supply
    5. 10.5 PCM5252 Power Modes
      1. 10.5.1 Setting Digital Power Supplies and I/O Voltage Rails
        1. 13.2.2 PLL Tables for Software Controlled Devices
      2. 10.5.2 Power Save Modes
        1. 13.2.1.3 Page 1 Registers
          1. 13.2.1.3.1 Page 1 / Register 1
          2. 13.2.1.3.2 Page 1 / Register 2
          3. 13.2.1.3.3 Page 1 / Register 5
          4. 13.2.1.3.4 Page 1 / Register 6
          5. 13.2.1.3.5 Page 1 / Register 7
          6. 13.2.1.3.6 Page 1 / Register 8
          7. 13.2.1.3.7 Page 1 / Register 9
        2. 13.2.1.4 Page 44 Registers
          1. 13.2.1.4.1 Page 44 / Register 1
        3. 13.2.1.5 Page 253 Registers
          1. 13.2.1.5.1 Page 253 / Register 63
          2. 13.2.1.5.2 Page 253 / Register 64
      3. 10.5.3 Power Save Parameter Programming
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 13.2.1.2.19 Page 0 / Register 24
      2. 13.2.1.2.20 Page 0 / Register 27
      3. 13.2.1.2.21 Page 0 / Register 28
      4. 13.2.1.2.22 Page 0 / Register 29
      5. 13.2.1.2.23 Page 0 / Register 30
      6. 13.2.1.2.24 Page 0 / Register 32
      7. 13.2.1.2.25 Page 0 / Register 33
      8. 13.2.1.2.26 Page 0 / Register 34
      9. 13.2.1.2.27 Page 0 / Register 35
      10. 13.2.1.2.28 Page 0 / Register 36
      11. 13.2.1.2.29 Page 0 / Register 37
      12. 13.2.1.2.30 Page 0 / Register 40
      13. 13.2.1.2.31 Page 0 / Register 41
      14. 13.2.1.2.32 Page 0 / Register 42
      15. 13.2.1.2.33 Page 0 / Register 43
      16. 13.2.1.2.34 Page 0 / Register 44
      17. 13.2.1.2.35 Page 0 / Register 59
      18. 13.2.1.2.36 Page 0 / Register 60
      19. 13.2.1.2.37 Page 0 / Register 61
      20. 13.2.1.2.38 Page 0 / Register 62
      21. 13.2.1.2.39 Page 0 / Register 63
      22. 13.2.1.2.40 Page 0 / Register 64
      23. 13.2.1.2.41 Page 0 / Register 65
      24. 13.2.1.2.42 Page 0 / Register 80
      25. 13.2.1.2.43 Page 0 / Register 81
      26. 13.2.1.2.44 Page 0 / Register 82
      27. 13.2.1.2.45 Page 0 / Register 83
      28. 13.2.1.2.46 Page 0 / Register 84
      29. 13.2.1.2.47 Page 0 / Register 85
      30. 13.2.1.2.48 Page 0 / Register 86
      31. 13.2.1.2.49 Page 0 / Register 87
      32. 13.2.1.2.50 Page 0 / Register 90
      33. 13.2.1.2.51 Page 0 / Register 91
      34. 13.2.1.2.52 Page 0 / Register 92
      35. 13.2.1.2.53 Page 0 / Register 93
      36. 13.2.1.2.54 Page 0 / Register 94
      37. 13.2.1.2.55 Page 0 / Register 95
      38. 13.2.1.2.56 Page 0 / Register 108
      39. 13.2.1.2.57 Page 0 / Register 109
      40. 13.2.1.2.58 Page 0 / Register 114
      41. 13.2.1.2.59 Page 0 / Register 115
      42. 13.2.1.2.60 Page 0 / Register 118
      43. 13.2.1.2.61 Page 0 / Register 119
      44. 13.2.1.2.62 Page 0 / Register 120
      45. 13.2.1.2.63 Page 0 / Register 121
      46. 13.2.1.2.64 Page 0 / Register 122
      47. 13.2.1.2.65 Page 0 / Register 123
      48. 13.2.1.2.66 Page 0 / Register 124
      49. 13.2.1.2.67 Page 0 / Register 125
    2. 11.2 Layout Example
  12. 12Programming
    1. 12.1 Coefficient Data Formats
    2. 12.2 Power Down and Reset Behavior
  13. 13Register Maps
    1. 13.1 PCM5252 Register Map
      1. 13.1.1 Detailed Register Descriptions
        1. 13.1.1.1 Register Map Summary
        2. 13.1.1.2 Page 0 Registers
        3. 13.1.1.3 Page 1 Registers
        4. 13.1.1.4 Page 44 Registers
        5. 13.1.1.5 Page 253 Registers
      2. 13.1.2 PLL Tables for Software Controlled Devices
  14. 14Device and Documentation Support
    1. 14.1 Community Resources
    2. 14.2 Trademarks
    3. 14.3 Electrostatic Discharge Caution
  15. 15Mechanical, Packaging, and Orderable Information
  16. 14Device and Documentation Support
    1. 14.1 Community Resources
    2. 14.2 Trademarks
    3. 14.3 Electrostatic Discharge Caution
  17. 15Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Power Supply Recommendations

10.1 Power Supply Distribution and Requirements

The PCM5252 devices are powered through the pins shown in Figure 75.

PCM5252 pcm5xxx_pwrtree.gif Figure 75. Power Distribution Tree Within PCM5252

Table 37. Power Supply Pin Descriptions

NAME USAGE / DESCRIPTION
AVDD Analog voltage supply; must be 3.3 V. This powers all analog circuitry that the DAC runs on.
DVDD Digital voltage supply. This is used as the I/O voltage control and the input to the onchip LDO.
CPVDD Charge Pump Voltage Supply - must be 3.3 V
LDOO Output from the onchip LDO. Should be used with a 0.1-µF decoupling cap. Can be driven (used as power input) with a 1.8-V supply to bypass the onchip LDO for lower power consumption.
AGND Analog ground
DGND Digital ground

10.2 Recommended Powerdown Sequence

Under certain conditions, the PCM5252 devices can exhibit some pops on power down. Pops are caused by a device not having enough time to detect power loss and start the muting process.

The PCM5252 devices have two auto-mute functions to mute the device upon power loss (intentional or unintentional).

10.2.1 XSMT = 0

When the XSMT pin is pulled low, the incoming PCM data is attenuated to 0, closely followed by a hard analog mute. This process takes 150 sample times (ts) + 0.2 ms.

Because this mute time is mainly dominated by the sampling frequency, systems sampling at 192 kHz will mute much faster than a 48-kHz system.

10.2.2 Clock Error Detect

When clock error is detected on the incoming data clock, the PCM5252 devices switch to an internal oscillator, and continue to the drive the output, while attenuating the data from the last known value. Once this process is complete, the PCM5252 outputs are hard muted to ground.

10.2.3 Planned Shutdown

These auto-muting processes can be manipulated by system designs to mute before power loss in the following ways:

  1. Assert XSMT low 150 tS + 0.2 ms before power is removed.
    2. PCM5252 f_pcm51xx_anti-pop_pwrdwn_seq.gif Figure 76. Assert XSMT
  2. Stop I2S clocks (SCK, BCK, LRCK) 3 ms before powerdown as shown in Figure 77.
    3. PCM5252 f_pcm51xx_anti-pop_pwrdwn_seq2.gif Figure 77. Stop I2C Clocks

10.2.4 Unplanned Shutdown

Many systems use a low-noise regulator to provide an AVDD 3.3-V supply for the DAC. The XSMT Pin can take advantage of such a feature to measure the pre-regulated output from the system SMPS to mute the output before the entire SMPS discharges. Figure 78 shows how to configure such a system to use the XSMT pin. The XSMT pin can also be used in parallel with a GPIO pin from the system microcontroller/DSP or power supply.

PCM5252 f_pcm51xx_xsmt_anti_pwrdwnpop.gif Figure 78. Using the XSMT Pin

10.3 External Power Sense Undervoltage Protection Mode

NOTE

External Power Sense Undervoltage Protection Mode is supported only when
DVDD = 3.3 V.

The XSMT pin can also be used to monitor a system voltage, such as the 24-VDC LCD TV backlight, or 12-VDC system supply using a voltage divider created with two resistors. (See Figure 79.)

  • If the XSMT pin makes a transition from 1 to 0 over 6 ms or more, the device switches into external undervoltage protection mode. This mode uses two trigger levels:
    • When the XSMT pin level reaches 2 V, soft mute process begins.
    • When the XSMT pin level reaches 1.2 V, analog mute engages, regardless of digital audio level, and shutdown begins. (DAC and related circuitry powers down).

A timing diagram to show this is shown in Figure 80.

NOTE

The XSMT input pin voltage range is from –0.3 V to DVDD + 0.3 V. The ratio of external resistors must produce a voltage within this input range. Any increase in power supply (such as power supply positive noise or ripple) can pull the XSMT pin higher than DVDD + 0.3 V.

For example, if the PCM5252 is monitoring a 12-V input, and dividing the voltage by 4, then the voltage at XSMT during ideal power supply conditions is 3.3 V. A voltage spike higher than 14.4 V causes a voltage greater than 3.6 V (DVDD + 0.3) on the XSMT pin, potentially damaging the device.

Providing the divider is set appropriately, any DC voltage can be monitored.

PCM5252 f_pcm51xx_xsmt_ext_uvp_ckt.gif Figure 79. XSMT in External UVP Mode
PCM5252 f_pcm51xx_td_xsmt_uvp.gif Figure 80. XSMT Timing for Undervoltage Protection

10.4 Power-On Reset Function

10.4.1 Power-On Reset, DVDD 3.3-V Supply

The PCM5252 includes a power-on reset function, as shown in Figure 81. With VDD > 2.8 V, the power-on reset function is enabled. After the initialization period, the PCM5252 is set to its default reset state. Analog output will begin ramping after valid data has been passing through the device for the given group delay given by the digital interpolation filter selected.

PCM5252 pcm512x4x_por_3p3.gif Figure 81. Power-On Reset Timing, DVDD = 3.3 V

10.4.2 Power-On Reset, DVDD 1.8-V Supply

The PCM5252 includes a power-on reset function, as shown in Figure 82. With AVDD greater than approximately 2.8 V, CPVDD greater than approximately 2.8 V, and DVDD greater than approximately 1.5 V, the power-on reset function is enabled. After the initialization period, the PCM5252 is set to its default reset state.

PCM5252 pcm512x4x_por_1p8.gif Figure 82. Power-On Reset Timing, DVDD = 1.8 V

10.5 PCM5252 Power Modes

10.5.1 Setting Digital Power Supplies and I/O Voltage Rails

The internal digital core of the PCM5252 devices run from a 1.8-V supply. This can be generated by the internal LDO, or by an external 1.8-V supply.

DVDD is used to set the I/O voltage, and to be used as the input to the onchip LDO that creates the 1.8 V required by the digital core.

For systems that require 3.3-V I/O support, but lower power consumption, DVDD should be connected to 3.3 V and LDOO can be connected to an external 1.8-V source. Doing so will disable the onchip LDO.

When setting I/O voltage to be 1.8 V, both DVDD and LDOO must be provided with an external 1.8-V supply.

10.5.2 Power Save Modes

The PCM5252 devices offer two power-save modes: standby and power-down.

When a clock error (SCK, BCK, and LRCK) or clock halt is detected, the PCM5252 device automatically enters standby mode. The DAC and line driver are also powered down. The device can also be placed in standby mode via software command.

When BCK and LRCK remain at a low level for more than 1 second, the PCM5252 device automatically enters powerdown mode. Power-down mode disables the negative charge pump and bias/reference circuit, in addition to those disabled in standby mode. The device can also be placed in power-down mode via software command.

The detection time of BCK and LRCK halt can be controlled by Page 0, Register 44, D(2:0).

When expected audio clocks (SCK, BCK, LRCK) are applied to the PCM5252 device, or if BCK and LRCK start correctly while SCK remains at ground level for 16 successive LRCK periods, the device starts its powerup sequence automatically.

10.5.3 Power Save Parameter Programming

Table 38. Power Save Registers

REGISTER DESCRIPTION
Page 0, Register 2, D(4) Software standby mode command
Page 0, Register 2, D(0) Software power-down command
Page 0, Register 2, D(4) and D(0) Software power-up sequence command (required after software standby or power-down)
Page 0, Register 44, D(2:0) Detection time of BCK and LRCK halt