SLVS077F April   1977  – January 2021 SG2524 , SG3524

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configurations and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
  7. 7 12
    1. 7.1 Electrical Characteristics
    2. 7.2 Electrical Characteristics — Continued, Both Parts
    3. 7.3 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 17
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Blanking
      2. 9.3.2 Error Amplifier
      3. 9.3.3 Compensation
      4. 9.3.4 Output Circuitry
      5. 9.3.5 Current Limiting
    4. 9.4 Device Functional Modes
      1. 9.4.1 Synchronous Operation
      2. 9.4.2 Shutdown Circuitry
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Feedback Traces
      2. 10.1.2 Input/Output Capacitors
      3. 10.1.3 Compensation Components
      4. 10.1.4 Traces and Ground Planes
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Related Links
    2. 11.2 Trademarks

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • NS|16
  • N|16
  • D|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information
10.2.1.2.2 Voltage Reference

The 5-V internal reference can be employed by use of an external resistor divider network to establish a reference common-mode voltage range (1.8 V to 3.4 V) within the error amplifiers (see Figure 10-5), or an external reference can be applied directly to the error amplifier. For operation from a fixed 5-V supply, the internal reference can be bypassed by applying the input voltage to both the VCC and VREF terminals. In this configuration, however, the input voltage is limited to a maximum of 6 V.

GUID-21A79D3C-638E-490F-97A1-3985D4B5AAFB-low.gifFigure 10-5 Error-Amplifier Bias Circuits