SCLS376I June 1997 – March 2015 SN54AHC273 , SN74AHC273
PRODUCTION DATA.
Refer to the PDF data sheet for device specific package drawings
These devices are positive-edge-triggered D-type
flip-flops with a direct clear (CLR) input.
Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When CLK is at either the high or low level, the D input has no effect at the output.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
SNx4AHC273 | PDIP (20) | 24.33 mm × 6.35 mm |
SSOP (20) | 7.20 mm × 5.30 mm | |
TSSOP (20) | 6.50 mm × 4.40 mm | |
TVSOP (20) | 5.00 mm × 4.40 mm | |
SOIC (20) | 12.80 mm × 7.50 mm |