These devices are positive-edge-triggered D-type
flip-flops with a direct clear (CLR) input.
Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When CLK is at either the high or low level, the D input has no effect at the output.
|Part number||Order||Technology Family||Input type||Output type||VCC (Min) (V)||VCC (Max) (V)||IOL (Max) (mA)||IOH (Max) (mA)||Rating||Package Group|
PDIP | 20
SOIC | 20
SO | 20
SSOP | 20
TSSOP | 20
TVSOP | 20
|SN54AHC273||Samples not available||AHC||CMOS||CMOS||2||5.5||50||-50||Military||
CDIP | 20
CFP | 20
LCCC | 20