SCLS041J December   1982  – October 2021 SN54HC595 , SN74HC595

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Operating Characteristics
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

3 Description

The SNx4HC595 devices contain an 8-bit, serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift and storage register. The shift register has a direct overriding clear (SRCLR) input, serial (SER) input, and serial outputs for cascading. When the output-enable (OE) input is high, the outputs are in the high-impedance state.

Device Information
PART NUMBER PACKAGE(1) BODY SIZE (NOM)
SN54HC595FK LCCC (20) 8.89 mm × 8.89 mm
SN54HC595J CDIP (16) 21.34 mm × 6.92 mm
SN74HC595N PDIP (16) 19.31 mm × 6.35 mm
SN74HC595D SOIC (16) 9.90 mm × 3.90 mm
SN74HC595DW SOIC (16) 10.30 mm × 7.50 mm
SN74HC595DB SSOP (16) 6.20 mm × 5.30 mm
SN74HC595PW TSSOP (16) 5.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at the end of the data sheet.
GUID-CFC41F3A-3CF2-46A9-B97B-313C2A957749-low.gifFunctional Block Diagram