SCAS992 March   2024 SN54SC8T595-SEP

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Characteristics
    7. 5.7 Switching Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 SCxT Enhanced Input Voltage
        1. 7.3.1.1 Down Translation
        2. 7.3.1.2 Up Translation
      2. 7.3.2 Balanced CMOS 3-State Outputs
      3. 7.3.3 Clamp Diode Structure
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Power Considerations
        2. 8.2.1.2 Input Considerations
        3. 8.2.1.3 Output Considerations
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information
    2. 11.2 Mechanical Data

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.6 Timing Characteristics

over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER DESCRIPTION CONDITION VCC -55°C to 125°C UNIT
MIN MAX
fCLOCK Clock frequency 1.2V 1.8 MHz
tW Pulse duration RCLK or SRCLK high or low 1.2V 57.4 ns
SCRCLR low 1.2V 47.3 ns
tSU Setup time SER before SRCLK↑ 1.2V 45.8 ns
SRCLK↑ before RCLK↑ 1.2V 169.4 ns
SRCLR low before RCLK↑ 1.2V 180.4 ns
SRCLR high (inactive) before SRCLK↑ 1.2V 61.2 ns
tH Hold time SER after SRCLK↑ 1.2V 0 ns
fCLOCK Clock frequency 1.8V 10.3 MHz
tW Pulse duration RCLK or SRCLK high or low 1.8V 15.7 ns
SCRCLR low 1.8V 13.5 ns
tSU Setup time SER before SRCLK↑ 1.8V 13.2 ns
SRCLK↑ before RCLK↑ 1.8V 44.4 ns
SRCLR low before RCLK↑ 1.8V 48.5 ns
SRCLR high (inactive) before SRCLK↑ 1.8V 10.1 ns
tH Hold time SER after SRCLK↑ 1.8V 0.8 ns
fCLOCK Clock frequency 2.5V 19.8 MHz
tW Pulse duration RCLK or SRCLK high or low 2.5V 10.9 ns
SCRCLR low 2.5V 10.9 ns
tSU Setup time SER before SRCLK↑ 2.5V 9.8 ns
SRCLK↑ before RCLK↑ 2.5V 25.3 ns
SRCLR low before RCLK↑ 2.5V 28.9 ns
SRCLR high (inactive) before SRCLK↑ 2.5V 6.8 ns
tH Hold time SER after SRCLK↑ 2.5V 0.6 ns
fCLOCK Clock frequency 3.3V 29.3 MHz
tW Pulse duration RCLK or SRCLK high or low 3.3V 9.6 ns
SCRCLR low 3.3V 9.7 ns
tSU Setup time SER before SRCLK↑ 3.3V 8.5 ns
SRCLK↑ before RCLK↑ 3.3V 18.7 ns
SRCLR low before RCLK↑ 3.3V 21.8 ns
SRCLR high (inactive) before SRCLK↑ 3.3V 5.7 ns
tH Hold time SER after SRCLK↑ 3.3V 0.5 ns
fCLOCK Clock frequency 5V 58.3 MHz
tW Pulse duration RCLK or SRCLK high or low 5V 9 ns
SCRCLR low 5V 9.2 ns
tSU Setup time SER before SRCLK↑ 5V 6.8 ns
SRCLK↑ before RCLK↑ 5V 14.5 ns
SRCLR low before RCLK↑ 5V 15.7 ns
SRCLR high (inactive) before SRCLK↑ 5V 5 ns
tH Hold time SER after SRCLK↑ 5V 0.4 ns