SLLSEI2A September   2017  – December 2017 SN55HVD233-SP

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Driver Electrical Characteristics
    6. 7.6  Receiver Electrical Characteristics
    7. 7.7  Driver Switching Characteristics
    8. 7.8  Receiver Switching Characteristics
    9. 7.9  Device Switching Characteristics
    10. 7.10 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Modes
      2. 9.3.2 Loopback
      3. 9.3.3 CAN Bus States
      4. 9.3.4 ISO 11898 Compliance of SN55HVD233-SP
        1. 9.3.4.1 Introduction
        2. 9.3.4.2 Differential Signal
          1. 9.3.4.2.1 Common-Mode Signal
        3. 9.3.4.3 Interoperability of 3.3-V CAN in 5-V CAN Systems
      5. 9.3.5 Thermal Shutdown
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Diagnostic Loopback
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Slope Control
        2. 10.2.2.2 Standby
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Bus Loading, Length, and Number of Nodes
      2. 12.1.2 CAN Termination
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Receiving Notification of Documentation Updates
    2. 13.2 Community Resources
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • HKX|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Parameter Measurement Information

SN55HVD233-SP pmi_dri_lls557.gif Figure 12. Driver Voltage, Current, and Test Definition
SN55HVD233-SP pmi_bus_lls557.gif Figure 13. Bus Logic State Voltage Definitions
SN55HVD233-SP pmi_driv_lls557.gif Figure 14. Driver VOD
SN55HVD233-SP pmi_dtc_lls557.gif
A. The input pulse is supplied by a generator having the following characteristics:
  • Pulse repetition rate (PRR) ≤125 kHz, 50% duty cycle
  • tr ≤ 6 ns
  • tf ≤ 6 ns
  • ZO = 50 Ω
B. CL includes fixture and instrumentation capacitance.
Figure 15. Driver Test Circuit and Voltage Waveforms
SN55HVD233-SP pmi_rece_lls557.gif Figure 16. Receiver Voltage and Current Definitions
SN55HVD233-SP pmi_rectc_lls557.gif
A. The input pulse is supplied by a generator having the following characteristics:
  • PRR ≤125 kHz, 50% duty cycle
  • tr ≤ 6 ns
  • tf ≤ 6 ns
  • ZO = 50 Ω
B. CL includes fixture and instrumentation capacitance.
Figure 17. Receiver Test Circuit and Voltage Waveforms

Table 2. Differential Input Voltage Threshold Test

INPUT OUTPUT MEASURED
VCANH VCANL R |VID|
–6.1 V –7 V L VOL 900 mV
12 V 11.1 V L 900 mV
–1 V –7 V L 6 V
12 V 6 V L 6 V
–6.5 V –7 V H VOH 500 mV
12 V 11.5 V H 500 mV
–7 V –1 V H 6 V
6 V 12 V H 6 V
Open Open H X
SN55HVD233-SP pmi_testc_sllsei2.gif

NOTE:

This test is conducted to test survivability only. Data stability at the R output is not specified.
Figure 18. Test Circuit, Transient Overvoltage Test
SN55HVD233-SP pmi_tens_sllsei2.gif

NOTE:

All VI input pulses are supplied by a generator having the following characteristics:
  • tr or tf ≤ 6 ns
  • PRR = 125 kHz, 50% duty cycle
Figure 19. Ten(s) Test Circuit and Voltage Waveforms
SN55HVD233-SP pmi_vocpp_LLSEI2.gif

NOTE:

All VI input pulses are supplied by a generator having the following characteristics:
  • tr or tf ≤ 6 ns
  • PRR = 125 kHz, 50% duty cycle
Figure 20. VOC(pp) Test Circuit and Voltage Waveforms
SN55HVD233-SP pmi_tloop_sllsei2.gif Figure 21. T(loop) Test Circuit and Voltage Waveforms
SN55HVD233-SP pmi_tlbk_LLSEI2.gif Figure 22. T(LBK) Test Circuit and Voltage Waveforms
SN55HVD233-SP pmi_los_lls557.gif Figure 23. IOS Test Circuit and Waveforms
SN55HVD233-SP pmi_comm_lls557.gif

NOTE:

All input pulses are supplied by a generator with ƒ ≤ 1.5 MHz.
Figure 24. Common-Mode Voltage Rejection