SLLSEA0I February   2012  – January 2021 SN6501

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Revision History
  4. 4 Pin Configuration and Functions
  5. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Handling Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Typical Characteristics
  6. 6 Parameter Measurement Information
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Push-Pull Converter
      2. 7.3.2 Core Magnetization
    4. 7.4 Device Functional Modes
      1. 7.4.1 Start-Up Mode
      2. 7.4.2 Operating Mode
      3. 7.4.3 Off-Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 SN6501 Drive Capability
        2. 8.2.2.2 LDO Selection
        3. 8.2.2.3 Diode Selection
        4. 8.2.2.4 Capacitor Selection
        5. 8.2.2.5 Transformer Selection
          1. 8.2.2.5.1 V-t Product Calculation
          2. 8.2.2.5.2 Turns Ratio Estimate
          3. 8.2.2.5.3 Recommended Transformers
      3. 8.2.3 Application Curve
      4. 8.2.4 Higher Output Voltage Designs
      5. 8.2.5 Application Circuits
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.6 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
tr-DD1, D2 output rise timeVCC = 3.3 V ± 10%, See Figure 6-470ns
VCC = 5 V ± 10%, See Figure 6-480
tf-DD1, D2 output fall timeVCC = 3.3 V ± 10%, See Figure 6-4110ns
VCC = 5 V ± 10%, See Figure 6-460
tBBMBreak-before-make timeVCC = 3.3 V ± 10%, See Figure 6-4150ns
VCC = 5 V ± 10%, See Figure 6-450