SLLS889C June   2008  – August 2016 SN65HVD1040A-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Power Dissipation Characteristics
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Operating Modes
        1. 9.3.1.1 Bus States by Mode
        2. 9.3.1.2 Normal Mode
        3. 9.3.1.3 Standby Mode and RXD Wake-Up Request
      2. 9.3.2 Protection Features
        1. 9.3.2.1 TXD Dominant State Time-Out
        2. 9.3.2.2 Thermal Shutdown
        3. 9.3.2.3 Undervoltage Lockout and Unpowered Device
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Using With 3.3-V Microcontrollers
      2. 10.1.2 Using SPLIT With Split Termination
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
        1. 10.2.1.1 Bus Loading, Length, and Number of Nodes
        2. 10.2.1.2 CAN Termination
        3. 10.2.1.3 Loop Propagation Delay
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Transient Voltage Suppresser (TVS) Diodes
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
    3. 12.3 ESD Protection
  13. 13Device and Documentation Support
    1. 13.1 Receiving Notification of Documentation Updates
    2. 13.2 Community Resource
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Parameter Measurement Information

SN65HVD1040A-Q1 dvr_tst_lls995.gif Figure 3. Driver Voltage, Current, and Test Definition
SN65HVD1040A-Q1 vod_tst_lls995.gif Figure 4. Driver VOD Test Circuit
SN65HVD1040A-Q1 drv_tst_wf_lls995.gif Figure 5. Driver Test Circuit and Voltage Waveforms
SN65HVD1040A-Q1 rx_v_cd_lls995.gif Figure 6. Receiver Voltage and Current Definitions
SN65HVD1040A-Q1 rx_tst_cx_waves_lls995.gif
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 125 kHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns, ZO = 50 Ω.
B. CL includes instrumentation and fixture capacitance within ±20%.
Figure 7. Receiver Test Circuit and Voltage Waveforms

Table 1. Differential Input Voltage Threshold Test

INPUT OUTPUT
R
VCANH VCANL |VID|
–11.1 V –12 V 900 mV L VOL
12 V 11.1 V 900 mV L
–6 V –12 V 6 V L
12 V 6 V 6 V L
–11.5 V –12 V 500 mV H VOH
12 V 11.5 V 500 mV H
–12 V –6 V 6 V H
6 V 12 V 6 V H
Open Open X H
SN65HVD1040A-Q1 ten_tc_wf_lls995.gif
A. CL = 100 pF and includes instrumentation and fixture capacitance within ±20%.
B. All VI input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 6 ns, pulse repetition rate (PRR) = 125 kHz, 50% duty cycle.
Figure 8. ten Test Circuit and Waveforms
SN65HVD1040A-Q1 comonmode_lls995.gif

NOTE:

All VI input pulses are from 0 V to VCC and supplied by a generator having the following characteristics: tr or tf ≤ 6 ns, pulse repetition rate (PRR) = 125 kHz, 50% duty cycle.
Figure 9. Common-Mode Output Voltage Test and Waveforms
SN65HVD1040A-Q1 tloop_tc_wf_lls995.gif
A. CL = 100 pF and includes instrumentation and fixture capacitance within ±20%.
B. All VI input pulses are from 0 V to VCC and supplied by a generator having the following characteristics: tr or tf ≤ 6 ns, pulse repetition rate (PRR) = 125 kHz, 50% duty cycle.
Figure 10. t(LOOP) Test Circuit and Waveforms
SN65HVD1040A-Q1 tm_out_wf_lls753_v2.gif
A. All VI input pulses are from 0 V to VCC and supplied by a generator having the following characteristics: tr or tf ≤ 6 ns, pulse repetition rate (PRR) = 500 Hz, 50% duty cycle.
B. CL = 100 pF includes instrumentation and fixture capacitance within ±20%.
Figure 11. Dominant Time-Out Test Circuit and Waveforms
SN65HVD1040A-Q1 drv_sc_wf_lls995.gif Figure 12. Driver Short-Circuit Current Test and Waveforms
SN65HVD1040A-Q1 pmi_tbus_test_wave_lls995.gif
A. For VI bit width ≤ 0.7 µs, VO = VOH. For VI bit width ≥ 5 µs, VO = VOL. VI input pulses are supplied from a generator with the following characteristics: tr/tf < 6 ns.
B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 13. tBUS Test Circuit and Waveforms
SN65HVD1040A-Q1 driver_out_sym_lls995.gif
A. All VI input pulses are from 0 V to VCC and supplied by a generator having the following characteristics: tr/tf ≤ 6 ns, pulse repetition rate (PRR) = 250 kHz, 50% duty cycle.
Figure 14. Driver Output Symmetry Test Circuit