SLLS877H December   2007  – March 2017 SN65HVD1780 , SN65HVD1781 , SN65HVD1782

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings: JEDEC
    3. 7.3 ESD Ratings: IEC
    4. 7.4 Recommended Operating Conditions
    5. 7.5 Thermal Information
    6. 7.6 Electrical Characteristics
    7. 7.7 Power Dissipation Characteristics
    8. 7.8 Switching Characteristics
    9. 7.9 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Equivalent Input Schematic
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 70-V Fault Protection
      2. 9.3.2 Receiver Failsafe
      3. 9.3.3 Hot-Plugging
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
        1. 10.2.1.1 Data Rate and Bus Length
        2. 10.2.1.2 Stub Length
        3. 10.2.1.3 Bus Loading
        4. 10.2.1.4 Receiver Failsafe
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Custom Design with WEBENCH® Tools
      3. 10.2.3 Application Curve
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Custom Design with WEBENCH® Tools
      2. 13.1.2 Third-Party Products Disclaimer
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Related Links
    4. 13.4 Receiving Notification of Documentation Updates
    5. 13.5 Community Resources
    6. 13.6 Trademarks
    7. 13.7 Electrostatic Discharge Caution
    8. 13.8 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Parameter Measurement Information

Input generator rate is 100 kbps, 50% duty cycle, rise or fall time is less than 6 ns, output impedance is 50 Ω.

SN65HVD1780 SN65HVD1781 SN65HVD1782 s0301-02_lls877.gif Figure 6. Measurement of Driver Differential Output Voltage With Common-Mode Load
SN65HVD1780 SN65HVD1781 SN65HVD1782 s0302-01_lls872.gif Figure 7. Measurement of Driver Differential and Common-Mode Output With RS-485 Load
SN65HVD1780 SN65HVD1781 SN65HVD1782 s0303-01_lls872.gif Figure 8. Measurement of Driver Differential Output Rise and Fall Times and Propagation Delays
SN65HVD1780 SN65HVD1781 SN65HVD1782 s0304-01_lls872.gif

NOTE:

D at 3 V to test non-inverting output, D at 0 V to test inverting output.
Figure 9. Measurement of Driver Enable and Disable Times With Active High Output and Pulldown Load
SN65HVD1780 SN65HVD1781 SN65HVD1782 s0305-01_lls872.gif

NOTE:

D at 0 V to test non-inverting output, D at 3 V to test inverting output.
Figure 10. Measurement of Driver Enable and Disable Times With Active-Low Output and Pullup Load
SN65HVD1780 SN65HVD1781 SN65HVD1782 s0306-01_lls872.gif Figure 11. Measurement of Receiver Output Rise and Fall Times and Propagation Delays
SN65HVD1780 SN65HVD1781 SN65HVD1782 s0307-01_lls872.gif Figure 12. Measurement of Receiver Enable and Disable Times With Driver Enabled
SN65HVD1780 SN65HVD1781 SN65HVD1782 s0308-01_lls872.gif Figure 13. SN65HVD1781 Measurement of Receiver Enable Times With Driver Disabled

8.1 Equivalent Input Schematic

When the input digital pins float, internal high value resistors pull D/REB pins to VCC and DE pin to GND to place the device into known states. If the voltage level of D/REB input pins is higher than that of power rail, input current can flow through the input resistor and pull up resistor to VCC.

SN65HVD1780 SN65HVD1781 SN65HVD1782 Equiv_input_schem_slls877.gif Figure 14. Equivalent Input Schematic Diagrams