SLLSEM1B February   2015  – April 2015 SN65LVDS93A-Q1

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 TTL Input Data
      2. 8.3.2 LVDS Output Data
    4. 8.4 Device Functional Modes
      1. 8.4.1 Input Clock Edge
      2. 8.4.2 Low Power Mode
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Power Up Sequence
        2. 9.2.2.2 Signal Connectivity
        3. 9.2.2.3 PCB Routing
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Board Stackup
      2. 11.1.2 Power and Ground Planes
      3. 11.1.3 Traces, Vias, and Other PCB Components
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Trademarks
    2. 12.2 Electrostatic Discharge Caution
    3. 12.3 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

11 Layout

11.1 Layout Guidelines

11.1.1 Board Stackup

There is no fundamental information about how many layers should be used and how the board stackup should look. Again, the easiest way the get good results is to use the design from the EVMs of Texas Instruments. The magazine Elektronik Praxis has published an article with an analysis of different board stackups. These are listed in Table 3. Generally, the use of microstrip traces needs at least two layers, whereas one of them must be a GND plane. Better is the use of a four-layer PCB, with a GND and a VCC plane and two signal layers. If the circuit is complex and signals must be routed as stripline, because of propagation delay and/or characteristic impedance, a six-layer stackup should be used.

Table 3. Possible Board Stackup on a Four-Layer PCB

MODEL 1 MODEL 2 MODEL 3 MODEL 4
Layer 1 SIG SIG SIG GND
Layer 2 SIG GND GND SIG
Layer 3 VCC VCC SIG VCC
Layer 4 GND SIG VCC SIG
Decoupling Good Good Bad Bad
EMC Bad Bad Bad Bad
Signal Integrity Bad Bad Good Bad
Self Disturbance Satisfaction Satisfaction Satisfaction High

11.1.2 Power and Ground Planes

A complete ground plane in high-speed design is essential. Additionally, a complete power plane is recommended as well. In a complex system, several regulated voltages can be present. The best solution is for every voltage to have its own layer and its own ground plane. But this would result in a huge number of layers just for ground and supply voltages. What are the alternatives? Split the ground planes and the power planes? In a mixed-signal design, e.g., using data converters, the manufacturer often recommends splitting the analog ground and the digital ground to avoid noise coupling between the digital part and the sensitive analog part. Take care when using split ground planes because:

  • Split ground planes act as slot antennas and radiate.
  • A routed trace over a gap creates large loop areas, because the return current cannot flow beside the signal, and the signal can induce noise into the nonrelated reference plane (Figure 21).
  • With a proper signal routing, crosstalk also can arise in the return current path due to discontinuities in the ground plane. Always take care of the return current (Figure 22).

For Figure 22, do not route a signal referenced to digital ground over analog ground and vice versa. The return current cannot take the direct way along the signal trace and so a loop area occurs. Furthermore, the signal induces noise, due to crosstalk (dotted red line) into the analog ground plane.

SN65LVDS93A-Q1 lacdpsrgs_SLLS846.gifFigure 21. Loop Area and Crosstalk Due to Poor Signal Routing and Ground Splitting
SN65LVDS93A-Q1 circp_SLLS846.gifFigure 22. Crosstalk Induced by the Return Current Path

11.1.3 Traces, Vias, and Other PCB Components

A right angle in a trace can cause more radiation. The capacitance increases in the region of the corner, and the characteristic impedance changes. This impedance change causes reflections.

  • Avoid right-angle bends in a trace and try to route them at least with two 45° corners. To minimize any impedance change, the best routing would be a round bend (see Figure 23).
  • Separate high-speed signals (e.g., clock signals) from low-speed signals and digital from analog signals; again, placement is important.
  • To minimize crosstalk not only between two signals on one layer but also between adjacent layers, route them with 90° to each other.

SN65LVDS93A-Q1 pgrab_SLLS846.gifFigure 23. Poor and Good Right Angle Bends

11.2 Layout Example

SN65LVDS93A-Q1 layoutex1_llsem1.gifFigure 24. SN65LVDS93A-Q1 EVM Top Layer – TSSOP Package
SN65LVDS93A-Q1 layoutex2_SLLS846.gifFigure 25. SN65LVDS93A-Q1 EVM VCC Layer – TSSOP Package