SLLSEH7B December   2013  – June 2016 SN65LVPE512

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
      1. 6.8.1 Case I Fixed Output and Variable Input Trace
      2. 6.8.2 Case II Fixed Input and Variable Output Trace+ 3-m Cable
      3. 6.8.3 Case III Fixed Input and Variable Output Trace (No Cable)
  7. 7 Parameter Measurement Information
    1. 7.1 Typical Eye Diagram and Performance Curves
    2. 7.2 Plot 1 Fixed Output Trace +3-m USB 3 Cable With Variable Input Trace
    3. 7.3 Plot 2 Fixed Input Trace With Variable Output Trace and +3-m USB 3.0 Cable
    4. 7.4 Plot 3 Fixed Input Trace With Variable Output Trace and (No Cable)
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Controller- and Connector-Side Pins
      2. 8.3.2 Programmable EQ, De-Emphasis and Amplitude Swing
      3. 8.3.3 Receiver Detection
        1. 8.3.3.1 At Power Up or Reset
        2. 8.3.3.2 During U2, U3 Link State
      4. 8.3.4 Electrical Idle Support
      5. 8.3.5 Signal Control Pin Setting
    4. 8.4 Device Functional Modes
      1. 8.4.1 Low Power Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

RGE Package
24-Pin VQFN
Top View
SN65LVPE512 po_RGE_SLLSEH7.gif
RMQ Package
24-Pin WQFN
Top View
SN65LVPE512 po_RLL_SLLSEH7.gif

Pin Functions

PIN I/O TYPE DESCRIPTION
NAME VQFN WQFN
HIGH SPEED DIFFERENTIAL I/O PINS
Controller_RX1– 8 19 I, CML Non-inverting and inverting CML differential input for CH1 and CH2. These pins are tied to an internal voltage bias by dual termination resistor circuit.
Pins labeled Controller must connect to the USB 3.0 host or device controller.
Pins labeled Connector must connect to the USB 3.0 connector.
Controller_RX1+ 9 20 I, CML
Connector_RX2– 20 8 I, CML
Connector_RX2+ 19 7 I, CML
Connector_TX1– 23 11 O, CML Non-inverting and inverting CML differential output for CH1 and CH2. These pins are tied to an internal voltage bias by termination resistors.
Pins labeled Controller must connect to the USB 3.0 host or device controller.
Pins labeled Connector must connect to the USB 3.0 connector.
Connector_TX1+ 22 10 O, CML
Controller_TX2– 11 22 O, CML
Controller_TX2+ 12 23 O, CML
DEVICE CONTROL PIN
EN_RXD 5 17 I, LVCMOS Sets device operation modes per Table 4. Internally pulled to VCC.
RSVD 14 — I, LVCMOS RSVD. Can be left as No-Connect.
NC 7, 24 1, 2, 6, 12, 18, 24 No-Connect Pads are not internally connected.
EQ CONTROL PINS(1)
DE1, DE2 3, 16 15, 4 I, LVCMOS Selects de-emphasis settings for CH1 and CH2 per Table 4. Internally tied to VCC/2
EQ1, EQ2 2, 17 14, 5 I, LVCMOS Selects equalization settings for CH1 and CH2 per Table 4. Internally tied to VCC/2
OS1, OS2 4, 15 16, NC (2) I, LVCMOS Selects output amplitude for CH1 and CH2 per Table 4. Internally tied to VCC/2
POWER PINS
VCC 1,13 3 Power Positive supply; must be 3.3 V ±10%
GND 6, 10, 18, 21, Thermal Pad 9, Thermal Pad Power Supply Ground
(1) Internally biased to VCC/2 with > 200-kΩ pullup or pulldown. When pins are left as NC board leakage at this pin pad must be < 1 µA otherwise drive to VCC/2 to assert mid-level state
(2) The RMQ has OS2 internally No-Connect, to select the 1042 mVpp level on TX2.