SCAS998 March   2024 SN74AHC594-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Characteristics
    7.     13
    8. 5.7 Switching Characteristics
    9. 5.8 Noise Characteristics
    10. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Balanced CMOS Push-Pull Outputs
      2. 7.3.2 Latching Logic
      3. 7.3.3 Standard CMOS Inputs
      4. 7.3.4 Wettable Flanks
      5. 7.3.5 Clamp Diode Structure
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
    3. 8.3 Design Requirements
      1. 8.3.1 Power Considerations
      2. 8.3.2 Input Considerations
      3. 8.3.3 Output Considerations
    4. 8.4 Detailed Design Procedure
    5. 8.5 Application Curves
    6. 8.6 Power Supply Recommendations
    7. 8.7 Layout
      1. 8.7.1 Layout Guidelines
      2. 8.7.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.6 Timing Characteristics

over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER DESCRIPTION CONDITION VCC TA = 25°C -40°C to 85°C -40°C to 125°C UNIT
MIN MAX MIN MAX MIN MAX
tH Hold time SER after SRCLK↑ 3.3 V ± 0.3 V 1.5 1.5 1.5 ns
tSU Setup time RCLR high 3.3 V ± 0.3 V 2.5 2.5 2.5 ns
SER before SRCLK↑ 3.3 V ± 0.3 V 3.5 3.5 3.5 ns
SRCLK↑ before RCLK↑ 3.3 V ± 0.3 V 8 8.5 8.5 ns
SRCLR high before SRCLK↑ 3.3 V ± 0.3 V 3 3 4 ns
SRCLR low before RCLK↑ 3.3 V ± 0.3 V 8 9 9 ns
tW Pulse duration RCLR low 3.3 V ± 0.3 V 5 5 5 ns
RCLK or SRCLK high or low 3.3 V ± 0.3 V 5 5 5.5 ns
RCLR or SRCLR low 3.3 V ± 0.3 V 5 5 5 ns
tH Hold time SER after SRCLK↑ 5 V ± 0.5 V 2 2 2 ns
tSU Setup time RCLR high 5 V ± 0.5 V 2.5 2.5 2.5 ns
SER before SRCLK↑ 5 V ± 0.5 V 3 3 3 ns
SRCLK↑ before RCLK↑ 5 V ± 0.5 V 5 5 5 ns
SRCLR high before SRCLK↑ 5 V ± 0.5 V 2.5 2.5 3.3 ns
SRCLR low before RCLK↑ 5 V ± 0.5 V 5 5 5 ns
tW Pulse duration RCLR low 5 V ± 0.5 V 5 5 5 ns
RCLK or SRCLK high or low 5 V ± 0.5 V 5 5 5 ns
RCLR or SRCLR low 5 V ± 0.5 V 5 5 5.2 ns