SCES530H December   2003  – December 2014 SN74AVC1T45

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Description (continued)
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Switching Characteristics: VCCA = 1.2 V
    7. 7.7  Switching Characteristics: VCCA = 1.5 V ± 0.1 V
    8. 7.8  Switching Characteristics: VCCA = 1.8 V ± 0.15 V
    9. 7.9  Switching Characteristics: VCCA = 2.5 V ± 0.2 V
    10. 7.10 Switching Characteristics: VCCA = 3.3 V ± 0.3 V
    11. 7.11 Operating Characteristics
    12. 7.12 Typical Characteristics
      1. 7.12.1 Typical Propagation Delay (A to B) vs Load Capacitance
      2. 7.12.2 Typical Propagation Delay (A to B) vs Load Capacitance
      3. 7.12.3 Typical Propagation Delay (A to B) vs Load Capacitance
      4. 7.12.4 Typical Propagation Delay (A to B) vs Load Capacitance
      5. 7.12.5 Typical Propagation Delay (A to B) vs Load Capacitance
  8. Parameter Measurement Information
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Fully Configurable Dual-Rail Design Allows Each Port to Operate Over the Full 1.2-V to 3.6-V Power-Supply Range
      2. 9.3.2 Support High-Speed Translation
      3. 9.3.3 Ioff Supports Partial-Power-Down Mode Operation
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Enable Times
    2. 10.2 Typical Applications
      1. 10.2.1 Unidirectional Logic Level-Shifting Application
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
        3. 10.2.1.3 Application Curve
      2. 10.2.2 Bidirectional Logic Level-Shifting Application
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
        3. 10.2.2.3 Application Curve
  11. 11Power Supply Recommendations
    1. 11.1 Power-Up Considerations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Trademarks
    2. 13.2 Electrostatic Discharge Caution
    3. 13.3 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DBV|6
  • DRL|6
  • YZP|6
  • DCK|6
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

10.1 Application Information

The SN74AVC1T45 device can be used in level-translation applications for interfacing devices or systems operating at different interface voltages with one another. The maximum data rate can be up to 500 Mbps when device translate signal from 1.8 V to 3.3 V.

10.1.1 Enable Times

Calculate the enable times for the SN74AVC1T45 using the following formulas:

  • tPZH (DIR to A) = tPLZ (DIR to B) + tPLH (B to A)
  • tPZL (DIR to A) = tPHZ (DIR to B) + tPHL (B to A)
  • tPZH (DIR to B) = tPLZ (DIR to A) + tPLH (A to B)
  • tPZL (DIR to B) = tPHZ (DIR to A) + tPHL (A to B)

In a bidirectional application, these enable times provide the maximum delay from the time the DIR bit is switched until an output is expected. For example, if the SN74AVC1T45 initially is transmitting from A to B, then the DIR bit is switched; the B port of the device must be disabled before presenting it with an input. After the B port has been disabled, an input signal applied to it appears on the corresponding A port after the specified propagation delay.

10.2 Typical Applications

10.2.1 Unidirectional Logic Level-Shifting Application

Figure 12 shows an example of the SN74AVC1T45 being used in a unidirectional logic level-shifting application.

app1_ces530.gifFigure 12. Unidirectional Logic Level-Shifting Application
PIN NAME FUNCTION DESCRIPTION
1 VCCA VCC1 SYSTEM-1 supply voltage (1.2 V to 3.6 V)
2 GND GND Device GND
3 A OUT Output level depends on VCC1 voltage.
4 B IN Input threshold value depends on VCC2 voltage.
5 DIR DIR GND (low level) determines B-port to A-port direction.
6 VCCB VCC2 SYSTEM-2 supply voltage (1.2 V to 3.6 V)

10.2.1.1 Design Requirements

For this design example, use the parameters listed in Table 2.

Table 2. Design Parameters

DESIGN PARAMETERS EXAMPLE VALUES
Input voltage range 1.2 V to 3.6 V
Output voltage range 1.2 V to 3.6 V

10.2.1.2 Detailed Design Procedure

To begin the design process, determine the following:

  • Input voltage range
    • Use the supply voltage of the device that is driving the SN74AVC1T45 device to determine the input voltage range. For a valid logic-high, the value must exceed the VIH of the input port. For a valid logic low the value must be less than the VIL of the input port.
  • Output voltage range
    • Use the supply voltage of the device that the SN74AVC1T45 device is driving to determine the output voltage range.

10.2.1.3 Application Curve

app-curve-1.gifFigure 13. Translation Up (1.2 V to 3.3 V) at 2.5 MHz

10.2.2 Bidirectional Logic Level-Shifting Application

Figure 14 shows the SN74AVC1T45 being used in a bidirectional logic level-shifting application. Because the SN74AVC1T45 does not have an output-enable (OE) pin, the system designer should take precautions to avoid bus contention between SYSTEM-1 and SYSTEM-2 when changing directions.

app2_ces530.gifFigure 14. Bidirectional Logic Level-Shifting Application

The following table shows data transmission from SYSTEM-1 to SYSTEM-2 and then from SYSTEM-2 to SYSTEM-1.

Table 3. Data Transmission: SYSTEM-1 and SYSTEM-2

STATE DIR CTRL I/O-1 I/O-2 DESCRIPTION
1 H Out In SYSTEM-1 data to SYSTEM-2
2 H Hi-Z Hi-Z SYSTEM-2 is getting ready to send data to SYSTEM-1. I/O-1 and I/O-2 are disabled. The bus-line state depends on pullup or pulldown.(1)
3 L Hi-Z Hi-Z DIR bit is flipped. I/O-1 and I/O-2 still are disabled. The bus-line state depends on pullup or pulldown.(1)
4 L In Out SYSTEM-2 data to SYSTEM-1
(1) SYSTEM-1 and SYSTEM-2 must use the same conditions, i.e., both pullup or both pulldown.

10.2.2.1 Design Requirements

Refer to Design Requirements.

10.2.2.2 Detailed Design Procedure

Refer to Detailed Design Procedure.

10.2.2.3 Application Curve

app-curve-2.gifFigure 15. Translation Up (1.2 V to 3.3 V) at 2.5 MHz