SCES530H December 2003 – December 2014 SN74AVC1T45
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
The SN74AVC1T45 device can be used in level-translation applications for interfacing devices or systems operating at different interface voltages with one another. The maximum data rate can be up to 500 Mbps when device translate signal from 1.8 V to 3.3 V.
Calculate the enable times for the SN74AVC1T45 using the following formulas:
In a bidirectional application, these enable times provide the maximum delay from the time the DIR bit is switched until an output is expected. For example, if the SN74AVC1T45 initially is transmitting from A to B, then the DIR bit is switched; the B port of the device must be disabled before presenting it with an input. After the B port has been disabled, an input signal applied to it appears on the corresponding A port after the specified propagation delay.
Figure 12 shows an example of the SN74AVC1T45 being used in a unidirectional logic level-shifting application.
|1||VCCA||VCC1||SYSTEM-1 supply voltage (1.2 V to 3.6 V)|
|3||A||OUT||Output level depends on VCC1 voltage.|
|4||B||IN||Input threshold value depends on VCC2 voltage.|
|5||DIR||DIR||GND (low level) determines B-port to A-port direction.|
|6||VCCB||VCC2||SYSTEM-2 supply voltage (1.2 V to 3.6 V)|
For this design example, use the parameters listed in Table 2.
|DESIGN PARAMETERS||EXAMPLE VALUES|
|Input voltage range||1.2 V to 3.6 V|
|Output voltage range||1.2 V to 3.6 V|
To begin the design process, determine the following:
Figure 14 shows the SN74AVC1T45 being used in a bidirectional logic level-shifting application. Because the SN74AVC1T45 does not have an output-enable (OE) pin, the system designer should take precautions to avoid bus contention between SYSTEM-1 and SYSTEM-2 when changing directions.
The following table shows data transmission from SYSTEM-1 to SYSTEM-2 and then from SYSTEM-2 to SYSTEM-1.
|1||H||Out||In||SYSTEM-1 data to SYSTEM-2|
|2||H||Hi-Z||Hi-Z||SYSTEM-2 is getting ready to send data to SYSTEM-1. I/O-1 and I/O-2 are disabled. The bus-line state depends on pullup or pulldown.(1)|
|3||L||Hi-Z||Hi-Z||DIR bit is flipped. I/O-1 and I/O-2 still are disabled. The bus-line state depends on pullup or pulldown.(1)|
|4||L||In||Out||SYSTEM-2 data to SYSTEM-1|
Refer to Design Requirements.
Refer to Detailed Design Procedure.