Single-Bit Dual-Supply Bus Transceiver with Configurable Voltage-Level Shifting and 3-State Outputs
Product details
Parameters
Package | Pins | Size
Features
- Available in the Texas Instruments NanoFree Package
- Fully Configurable Dual-Rail Design Allows Each Port to
Operate Over the Full 1.2-V to 3.6-V Power-Supply Range - VCC Isolation Feature - If Either VCC
Input Is At GND, Both Ports Are In The High-Impedance State - DIR Input Circuit Referenced to VCCA
- ±12-mA Output Drive at 3.3 V
- I/Os Are 4.6-V Tolerant
- Ioff Supports Partial-Power-Down Mode Operation
- Typical Max Data Rates
- 500 Mbps (1.8-V to 3.3-V Translation)
- 320 Mbps (<1.8-V to 3.3-V Translation)
- 320 Mbps (Translate to 2.5 V or 1.8 V)
- 280 Mbps (Translate to 1.5 V)
- 240 Mbps (Translate to 1.2 V)
- Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
- ESD Protection Exceeds JESD 22
- ±2000-V Human Body Model (A114-A)
- 200-V Machine Model (A115-A)
- ±1000-V Charged-Device Model (C101)
Description
This single-bit noninverting bus transceiver uses two separate configurable power-supply rails. The SN74AVC1T45 is optimized to operate with VCCA/VCCB set at 1.4 V to 3.6 V. It is operational with VCCA/VCCB as low as 1.2 V. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.2 V to 3.6 V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.2 V to 3.6 V. This allows for universal low-voltage, bidirectional translation between any of the 1.2-V, 1.5-V, 1.8-V, 2.5-V, and 3.3-V voltage nodes.
The SN74AVC1T45 is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR) input activate either the B-port outputs or the A-port outputs. The device transmits data from the A bus to the B bus when the B-port outputs are activated and from the B bus to the A bus when the A-port outputs are activated. The input circuitry on both A and B ports always is active and must have a logic HIGH or LOW level applied to prevent excess ICC and ICCZ.
The SN74AVC1T45 is designed so that the DIR input is powered by VCCA.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
The VCC isolation feature ensures that if either VCC input is at GND, then both ports are in the high-impedance state.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
Technical documentation
Design & development
For additional terms or required resources, click any title below to view the detail page where available.Hardware development
Description
Features
- Board design allows for versatility in evaluation
- Supports a wide-range of logic devices
Description
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Features
- SMB connector available for high speed operation
- Ground port available on each header pin to maintain signal integrity
- DIR and OE have 10K ohm pull up /pull down resistor options
- Designed to support up to 20 different devices
Description
Features
- Ultra-low power operation
- Single high-performance phase-locked-loop
- Supports mixed power supply operation from 1.8 V to 3.3 V
- Integrated EEPROM with two pages
- General purpose inputs and outputs for individual output enable and status signals
- Output divider synchronization and digital delays
Description
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- Onboard LED Driver with 0-5A LED Driver
- Simultaneous RGB LED operation
- High speed pattern display with native DLP4500 resolution (912x1140)
- Up to 4225 Hz binary pattern rate
- Up to 120 Hz 8-bit grayscale pattern rate
- Image or video display up to WXGA resolution (...)
Description
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Features
- Display images or video up to 1080p resolution (1920x1080 array)
- High speed patterns using the DLPC900
- Up to 9,523 Hz binary pattern rate
- Up to 247 Hz 8-bit grayscale pattern rate
- 2 Configurable I/O trigger for synchronizing with cameras, sensors, or other peripherals
- USB 1.1, HDMI and I2C interfaces
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Description
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Features
DLP9000
- Development- LightCrafter 9000 EVM
- Maximum Bandwidth- >40 Gbps
- Maximum Binary Pattern Rate- 9.5 kHZ
- DLP Digital Controller-DLPC900
- DLP PROM-DLPR900
- Wavelength Range- 400-700 nm
- Micromirror Array Size- 2560 x 1600
- Display Resolution- WQXGA
- Micromirror Array Diagonal- 0.9 inches
- Micromirror Pixel Pitch (...)
Description
Features
- 2GB DDR3L
- LP8733/LP8732 Power Solution
- On-board eMMC, NAND, NOR
- USB3, USB2, PCIe, Ethernet, COM8Q, CAN, MLB, MicroSD and HDMI connectors
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- LP8733/LP8732 Power Solution
- On-board eMMC, NAND, NOR
- USB3, USB2, PCIe, Ethernet, COM8Q, CAN, MLB, MicroSD and HDMI connectors
Description
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Features
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- 2-GByte DDR3L with ECC
- TPS659118 PMIC
- Audio and Serial expansion headers
- Processor SDK Linux and TI-RTOS support
- Supports Gigabit Ethernet
Description
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Features
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- 2-GByte DDR3L with ECC
- TPS65911A PMIC
- Audio and serial expansion headers
- Processor SDK Linux and TI-RTOS support
Description
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Features
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- 2-GByte DDR3L with ECC
- TPS65911A PMIC
- Audio and serial expansion headers
- Processor SDK Linux and TI-RTOS support
Description
Features
- 1.85/3.3V bidrectional conversion
- Compatible with TI Launchpads
- Wi-Fi Video Streaming
Design tools & simulation
Reference designs
CAD/CAE symbols
| Package | Pins | Download |
|---|---|---|
| DSBGA (YZP) | 6 | View options |
| SC70 (DCK) | 6 | View options |
| SOT-23 (DBV) | 6 | View options |
| SOT-5X3 (DRL) | 6 | View options |
Ordering & quality
Support & training
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