SN74AVC1T45

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DSBGA (YZP)

6

2 mm² .928 x 1.428

SOT-23 (DBV)

6

5 mm² 2.9 x 1.6

SOT-5X3 (DRL)

6

2 mm² 1.65 x 1.2

SOT-SC70 (DCK)

6

4 mm² 2 x 2.1

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Available in the Texas Instruments NanoFree Package
Fully Configurable Dual-Rail Design Allows Each Port to
Operate Over the Full 1.2-V to 3.6-V Power-Supply Range
V_CC Isolation Feature - If Either V_CC
Input Is At GND, Both Ports Are In The High-Impedance State
DIR Input Circuit Referenced to V_CCA
±12-mA Output Drive at 3.3 V
I/Os Are 4.6-V Tolerant
I_off Supports Partial-Power-Down Mode Operation
Typical Max Data Rates
- 500 Mbps (1.8-V to 3.3-V Translation)
- 320 Mbps (<1.8-V to 3.3-V Translation)
- 320 Mbps (Translate to 2.5 V or 1.8 V)
- 280 Mbps (Translate to 1.5 V)
- 240 Mbps (Translate to 1.2 V)
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
ESD Protection Exceeds JESD 22
- ±2000-V Human Body Model (A114-A)
- 200-V Machine Model (A115-A)
- ±1000-V Charged-Device Model (C101)

Available in the Texas Instruments NanoFree Package
Fully Configurable Dual-Rail Design Allows Each Port to
Operate Over the Full 1.2-V to 3.6-V Power-Supply Range
V_CC Isolation Feature - If Either V_CC
Input Is At GND, Both Ports Are In The High-Impedance State
DIR Input Circuit Referenced to V_CCA
±12-mA Output Drive at 3.3 V
I/Os Are 4.6-V Tolerant
I_off Supports Partial-Power-Down Mode Operation
Typical Max Data Rates
- 500 Mbps (1.8-V to 3.3-V Translation)
- 320 Mbps (<1.8-V to 3.3-V Translation)
- 320 Mbps (Translate to 2.5 V or 1.8 V)
- 280 Mbps (Translate to 1.5 V)
- 240 Mbps (Translate to 1.2 V)
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
ESD Protection Exceeds JESD 22
- ±2000-V Human Body Model (A114-A)
- 200-V Machine Model (A115-A)
- ±1000-V Charged-Device Model (C101)

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This single-bit noninverting bus transceiver uses two separate configurable power-supply rails. The SN74AVC1T45 is optimized to operate with V_CCA/V_CCB set at 1.4 V to 3.6 V. It is operational with V_CCA/V_CCB as low as 1.2 V. The A port is designed to track V_CCA. V_CCA accepts any supply voltage from 1.2 V to 3.6 V. The B port is designed to track V_CCB. V_CCB accepts any supply voltage from 1.2 V to 3.6 V. This allows for universal low-voltage, bidirectional translation between any of the 1.2-V, 1.5-V, 1.8-V, 2.5-V, and 3.3-V voltage nodes.

The SN74AVC1T45 is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR) input activate either the B-port outputs or the A-port outputs. The device transmits data from the A bus to the B bus when the B-port outputs are activated and from the B bus to the A bus when the A-port outputs are activated. The input circuitry on both A and B ports always is active and must have a logic HIGH or LOW level applied to prevent excess I_CC and I_CCZ.

The SN74AVC1T45 is designed so that the DIR input is powered by V_CCA.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The V_CC isolation feature ensures that if either V_CC input is at GND, then both ports are in the high-impedance state.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This single-bit noninverting bus transceiver uses two separate configurable power-supply rails. The SN74AVC1T45 is optimized to operate with V_CCA/V_CCB set at 1.4 V to 3.6 V. It is operational with V_CCA/V_CCB as low as 1.2 V. The A port is designed to track V_CCA. V_CCA accepts any supply voltage from 1.2 V to 3.6 V. The B port is designed to track V_CCB. V_CCB accepts any supply voltage from 1.2 V to 3.6 V. This allows for universal low-voltage, bidirectional translation between any of the 1.2-V, 1.5-V, 1.8-V, 2.5-V, and 3.3-V voltage nodes.

The SN74AVC1T45 is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR) input activate either the B-port outputs or the A-port outputs. The device transmits data from the A bus to the B bus when the B-port outputs are activated and from the B bus to the A bus when the A-port outputs are activated. The input circuitry on both A and B ports always is active and must have a logic HIGH or LOW level applied to prevent excess I_CC and I_CCZ.

The SN74AVC1T45 is designed so that the DIR input is powered by V_CCA.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The V_CC isolation feature ensures that if either V_CC input is at GND, then both ports are in the high-impedance state.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

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Technical documentation

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	Type	Title	Date
*	Data sheet	SN74AVC1T45 Single-Bit Dual-Supply Bus Transceiver with Configurable Voltage Translation and 3-State Outputs datasheet (Rev. H)	23 Dec 2014
	User guide	Generic AVC and LVC Direction Controlled Translation EVM (Rev. B)	30 Jul 2021
	Selection guide	Voltage Translation Buying Guide (Rev. A)	15 Apr 2021
	Selection guide	Logic Guide (Rev. AB)	12 Jun 2017
	Application note	Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)	02 Dec 2015
	Application note	Voltage Translation Between 3.3-V, 2.5-V, 1.8-V, and 1.5-V Logic Standards (Rev. B)	30 Apr 2015
	Test report	TI Power Reference Design for Xilinx® Artix®-7 (AC701)	12 May 2014
	User guide	PMP7977 User's Guide	11 Sep 2013
	User guide	LOGIC Pocket Data Book (Rev. B)	16 Jan 2007
	Application note	Semiconductor Packing Material Electrostatic Discharge (ESD) Protection	08 Jul 2004
	Application note	Selecting the Right Level Translation Solution (Rev. A)	22 Jun 2004
	More literature	Logic Cross-Reference (Rev. A)	07 Oct 2003
	More literature	LCD Module Interface Application Clip	09 May 2003
	User guide	AVC Advanced Very-Low-Voltage CMOS Logic Data Book, March 2000 (Rev. C)	20 Aug 2002
	More literature	Standard Linear & Logic for PCs, Servers & Motherboards	13 Jun 2002
	Application note	16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)	22 May 2002
	Application note	Dynamic Output Control (DOC) Circuitry Technology And Applications (Rev. B)	07 Jul 1999
	Application note	AVC Logic Family Technology and Applications (Rev. A)	26 Aug 1998

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