SCES530H December   2003  – December 2014 SN74AVC1T45

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Description (continued)
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Switching Characteristics: VCCA = 1.2 V
    7. 7.7  Switching Characteristics: VCCA = 1.5 V ± 0.1 V
    8. 7.8  Switching Characteristics: VCCA = 1.8 V ± 0.15 V
    9. 7.9  Switching Characteristics: VCCA = 2.5 V ± 0.2 V
    10. 7.10 Switching Characteristics: VCCA = 3.3 V ± 0.3 V
    11. 7.11 Operating Characteristics
    12. 7.12 Typical Characteristics
      1. 7.12.1 Typical Propagation Delay (A to B) vs Load Capacitance
      2. 7.12.2 Typical Propagation Delay (A to B) vs Load Capacitance
      3. 7.12.3 Typical Propagation Delay (A to B) vs Load Capacitance
      4. 7.12.4 Typical Propagation Delay (A to B) vs Load Capacitance
      5. 7.12.5 Typical Propagation Delay (A to B) vs Load Capacitance
  8. Parameter Measurement Information
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Fully Configurable Dual-Rail Design Allows Each Port to Operate Over the Full 1.2-V to 3.6-V Power-Supply Range
      2. 9.3.2 Support High-Speed Translation
      3. 9.3.3 Ioff Supports Partial-Power-Down Mode Operation
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Enable Times
    2. 10.2 Typical Applications
      1. 10.2.1 Unidirectional Logic Level-Shifting Application
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
        3. 10.2.1.3 Application Curve
      2. 10.2.2 Bidirectional Logic Level-Shifting Application
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
        3. 10.2.2.3 Application Curve
  11. 11Power Supply Recommendations
    1. 11.1 Power-Up Considerations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Trademarks
    2. 13.2 Electrostatic Discharge Caution
    3. 13.3 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DBV|6
  • DRL|6
  • YZP|6
  • DCK|6
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9 Detailed Description

9.1 Overview

The SN74AVC1T45 is single-bit, dual-supply, noninverting voltage level translation. Pin A and direction control pin are support by VCCA and pin B is support by VCCB. The A port is able to accept I/O voltages ranging from 1.2 V to 3.6 V, while the B port can accept I/O voltages from 1.2 to 3.6 V. The high on DIR allows data transmission from A to B and a low on DIR allows data transmission from B to A.

9.2 Functional Block Diagram

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9.3 Feature Description

9.3.1 Fully Configurable Dual-Rail Design Allows Each Port to Operate Over the Full 1.2-V to 3.6-V Power-Supply Range

Both VCCA and VCCB can be supplied at any voltage between 1.2 V and 3.6 V making the device suitable for translating between any of the voltage nodes (1.2-V, 1.8-V, 2.5-V and 3.3-V).

9.3.2 Support High-Speed Translation

SN74AVC1T45 can support high data-rate application. The translated signal data rate can be up to 500 Mbps when signal is translated from 1.8 V to 3.3 V.

9.3.3 Ioff Supports Partial-Power-Down Mode Operation

Ioff will prevent backflow current by disabling I/O output circuits when device is in partial-power-down mode.

9.4 Device Functional Modes

Table 1. Function Table(1)

INPUT
DIR
OPERATION
L B data to A bus
H A data to B bus
(1) Input circuits of the data I/Os always are active.