SCLS467F FEBRUARY   2003  – June 2016 SN74LV123A-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements — VCC = 3.3 V ± 0.3 V
    7. 6.7  Timing Requirements — VCC = 5 V ± 0.5 V
    8. 6.8  Switching Characteristics — VCC = 3.3 V ± 0.3 V
    9. 6.9  Switching Characteristics — VCC = 5 V ± 0.5 V
    10. 6.10 Operating Characteristics
    11. 6.11 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Power-Down Considerations
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Output Pulse Duration
        2. 9.2.1.2 Retriggering Data
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PW|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

PW Package
16-Pin TSSOP
Top View

Pin Functions

PIN I/O DESCRIPTION
NO. NAME
1 1A I Channel 1 falling edge trigger input when 1B = L; Hold low for other input methods
2 1B I Channel 1 rising edge trigger input when 1A = H; Hold high for other input methods
3 1CLR I Channel 1 rising edge trigger when 1A = H and 1B = L; Hold high for other input methods; Can cut pulse length short by driving low during output
4 1Q O Channel 1 inverted output
5 2Q O Channel 2 output
6 2Cext — Channel 2 external capacitor negative connection
7 2Rext/Cext — Channel 2 external capacitor and resistor junction connection
8 GND — Ground
9 2A I Channel 2 falling edge trigger input when 2B = L; Hold low for other input methods
10 2B I Channel 2 rising edge trigger input when 2A = H; Hold high for other input methods
11 2CLR I Channel 2 rising edge trigger when 2A = H and 2B = L; Hold high for other input methods; Can cut pulse length short by driving low during output
12 2Q O Channel 2 inverted output
13 1Q O Channel 1 output
14 1Cext — Channel 1 external capacitor negative connection
15 1Rext/Cext — Channel 1 external capacitor and resistor junction connection
16 VCC — Power supply