SCES124N December   1997  – January 2016 SN74LV125A

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Simplified Schematic
  5. Revision History
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Switching Characteristics, VCC = 2.5 V ± 0.2 V
    7. 7.7  Switching Characteristics, VCC = 3.3 V ± 0.3 V
    8. 7.8  Switching Characteristics, VCC = 5 V ± 0.5 V
    9. 7.9  Noise Characteristics
    10. 7.10 Operating Characteristics
    11. 7.11 Typical Characteristics
  8. Parameter Measurement Information
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Related Links
    2. 13.2 Trademarks
    3. 13.3 Electrostatic Discharge Caution
    4. 13.4 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|14
  • RGY|14
  • DB|14
  • DGV|14
  • PW|14
  • N|14
  • NS|14
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • 2-V to 5.5-V VCC Operation
  • Max tpd of 6 ns at 5 V
  • Typical VOLP (Output Ground Bounce)
    < 0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot)
    > 2.3 V at VCC = 3.3 V, TA = 25°C
  • Support Mixed-Mode Voltage Operation on
    All Ports
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 250 mA Per
    JESD 17
  • ESD Protection Exceeds JESD 22
    • 4000-V Human-Body Model
    • 200-V Machine Model
    • 2000-V Charged-Device Model

2 Applications

  • Flow Meters
  • Solid State Drives (SSDs): Enterprise
  • Power Over Ethernet (PoE)
  • Programmable Logic Controllers
  • Motor Drives and Controls
  • Electronic Points of Sale

3 Description

The SN74LV125A quadruple bus buffer gate is designed for 2-V to 5.5-V VCC operation.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
SN74LV125A TVSOP (14) 3.60 mm x 4.40 mm
SOIC (14) 8.65 mm × 3.91 mm
SOP (14) 10.30mm x 5.30 mm
SSOP (14) 6.20 mm x 5.30 mm
TSSOP (14) 5.00 mm x 4.40 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

4 Simplified Schematic

SN74LV125A logic_ces124.gif