SN74LV125A

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Quadruple bus buffer gates with 3-state outputs

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Product details

Parameters

Technology Family LV-A VCC (Min) (V) 2 VCC (Max) (V) 5.5 Channels (#) 4 IOL (Max) (mA) 16 ICC (Max) (uA) 20 IOH (Max) (mA) -16 Input type Standard CMOS Output type 3-State Features Balanced outputs, Very high speed (tpd 5-10ns), Partial power down (Ioff), Over-voltage tolerant inputs Data rate (Mbps) 220 Rating Catalog open-in-new Find other Non-Inverting buffer/driver

Package | Pins | Size

PDIP (N) 14 181 mm² 19.3 x 9.4 SOIC (D) 14 52 mm² 8.65 x 6 SOP (NS) 14 80 mm² 10.2 x 7.8 SSOP (DB) 14 48 mm² 6.2 x 7.8 TSSOP (PW) 14 32 mm² 5 x 6.4 TVSOP (DGV) 14 23 mm² 3.6 x 6.4 VQFN (RGY) 14 12 mm² 3.5 x 3.5 open-in-new Find other Non-Inverting buffer/driver

Features

  • 2-V to 5.5-V VCC Operation
  • Max tpd of 6 ns at 5 V
  • Typical VOLP (Output Ground Bounce)
    < 0.8 V at VCC = 3.3 V, TA = 5°C
  • Typical VOHV (Output VOH Undershoot)
    > 2.3 V at VCC = 3.3 V, TA = 25°C
  • Support Mixed-Mode Voltage Operation on
    All Ports
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 250 mA Per
    JESD 17
  • ESD Protection Exceeds JESD 22
    • 4000-V Human-Body Model
    • 200-V Machine Model
    • 2000-V Charged-Device Model
open-in-new Find other Non-Inverting buffer/driver

Description

The SN74LV125A quadruple bus buffer gate is designed for 2-V to 5.5-V VCC operation.

open-in-new Find other Non-Inverting buffer/driver
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Technical documentation

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Type Title Date
* Datasheet SN74LV125A Quadruple Bus Buffer Gates With 3-State Outputs datasheet (Rev. N) Jan. 19, 2016

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARDS Download
document-generic User guide
10
Description
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices
EVALUATION BOARDS Download
document-generic User guide
20
Description
Flexible EVM designed to support any logic or translation device that has a BQA, BQB, RGY (14-24 pin), RSV, RJW, or RHL package.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic and translation devices with included dual supply support
  • Board has 9 sections that can be broken apart for a smaller form factor

Design tools & simulation

SIMULATION MODELS Download
SCEJ247.ZIP (106 KB) - HSpice Model
SIMULATION MODELS Download
SCEM126.ZIP (18 KB) - IBIS Model
SIMULATION MODELS Download
SCEM657.ZIP (7 KB) - PSpice Model

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document-generic Schematic document-generic User guide

CAD/CAE symbols

Package Pins Download
PDIP (N) 14 View options
SO (NS) 14 View options
SOIC (D) 14 View options
SSOP (DB) 14 View options
TSSOP (PW) 14 View options
TVSOP (DGV) 14 View options
VQFN (RGY) 14 View options

Ordering & quality

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