SCLS744B
December 2013 – June 2022
SN74LV1T126
PRODUCTION DATA
1
Features
2
Applications
3
Description
4
Revision History
5
Related Products
6
Pin Configuration and Functions
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings
7.3
Recommended Operating Conditions
7.4
Thermal Information
7.5
Electrical Characteristics
7.6
Switching Characteristics
7.7
Operating Characteristics
7.8
Typical Characteristics
8
Parameter Measurement Information
9
Detailed Description
9.1
Overview
9.2
Functional Block Diagram
9.3
Feature Description
9.3.1
Clamp Diode Structure
9.3.2
Balanced CMOS Push-Pull Outputs
9.3.3
LVxT Enhanced Input Voltage
9.3.3.1
Down Translation
9.3.3.2
Up Translation
9.4
Device Functional Modes
10
Power Supply Recommendations
11
Layout
11.1
Layout Guidelines
12
Device and Documentation Support
12.1
Receiving Notification of Documentation Updates
12.2
Support Resources
12.3
Trademarks
12.4
Electrostatic Discharge Caution
12.5
Glossary
13
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
DCK|5
MPDS025G
DBV|5
MPDS018Q
Thermal pad, mechanical data (Package|Pins)
Orderable Information
scls744b_oa
scls744b_pm
1
Features
Single-supply voltage translator at 5-V, 3.3-V, 2.5-V, and 1.8-V V
CC
Operating range of 1.8 V to 5.5 V
Up translation:
1.2 V
(1)
to 1.8 V at 1.8-V V
CC
1.5 V
(1)
to 2.5 V at 2.5-V V
CC
1.8 V
(1)
to 3.3 V at 3.3-V V
CC
3.3 V to 5.0 V at 5.0-V V
CC
Down translation:
3.3 V to 1.8 V at 1.8-V V
CC
3.3 V to 2.5 V at 2.5-V V
CC
5.0 V to 3.3 V at 3.3-V V
CC
Logic output is referenced to V
CC
Output drive:
8 mA output drive at 5 V
7 mA output drive at 3.3 V
3 mA output drive at 1.8 V
Characterized up to 50 MHz at 3.3-V V
CC
5V Tolerance on input pins
–40°C to 125°C operating temperature range
Latch-Up Performance Exceeds 250 mAPer JESD 17
Supports standard logic pinouts
CMOS output B compatible with AUP1G and LVC1G families
(1)
1.
Refer to the V
IH
/V
IL
and output drive for lower V
CC
condition.