SCLS903 May 2022 SN74LV1T34-Q1
Refer to the PDF data sheet for device specific package drawings
Input signals can be up translated using the SN74LV1T34-Q1. The voltage applied at VCC will determine the output voltage and the input thresholds as described in the Recommended Operating Conditions and Electrical Characteristics tables. When connected to a high-impedance input, the output voltage will be approximately VCC in the HIGH state, and 0 V in the LOW state.
The inputs have reduced thresholds that allow for input high-state levels which are much lower than standard values. For example, standard CMOS inputs for a device operating at a 5-V supply will have a VIH(MIN) of 3.5 V. For the SN74LV1T34-Q1, VIH(MIN) with a 5-V supply is only 2 V, which would alow for up-translation from a typical 2.5-V to 5-V signals.
Ensure that the input signals in the HIGH state are above VIH(MIN) and input signals in the LOW state are lower than VIL(MAX) as shown in Figure 8-3.
Up Translation Combinations: