SCLS987D September   2023  – March 2024 SN74LV8T594-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Thermal Information
    4. 5.4 Recommended Operating Conditions
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Characteristics
    7.     13
    8. 5.7 Switching Characteristics
    9. 5.8 Noise Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Device Functional Modes
  9. 8 Feature Description
    1. 8.1 Balanced CMOS Push-Pull Outputs
    2. 8.2 Latching Logic with Known Power-Up State
    3. 8.3 LVxT Enhanced Input Voltage
    4. 8.4 Clamp Diode Structure
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Power Considerations
        2. 9.2.1.2 Input Considerations
        3. 9.2.1.3 Output Considerations
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • BQB|16
  • PW|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3 Device Functional Modes

Function Table lists the functional modes of the SN74LV8T594-Q1.

Table 7-1 Function Table
INPUTS(1) FUNCTION
SER SRCLK SRCLR RCLK RCLR
X X X X L Output register is cleared; all values set to low state.
X X L X X Shift register is cleared; all values set to low state.
L ↑ H X X First bit of the internal shift register set to low state.
Each subsequent register stores the data from the previous register.
H ↑ H X X First bit of the internal shift register set to high state.
Each subsequent register stores the data from the previous register.
X L, H, ↓ H ↑ X Values from internal shift register are loaded into the output register
Internal shift register values are not modified.
L ↑(2) H ↑(2) H Values from the internal shift register are loaded into the output register, then the first bit of the internal shift register is set to the low state.
Each subsequent shift register stores the data from the previous register.
H ↑(2) H ↑(2) H Values from the internal shift register are loaded into the output register, then the first bit of the internal shift register is set to the high state.
Each subsequent shift register stores the data from the previous register.
(1) H = High Voltage Level, L = Low Voltage Level, X = Don't Care
(2) For this mode of operation, SRCLK and RCLK are directly connected together.
Table 7-2 Latched Logic Power-Up State
Latch or Register Power-Up State(1)
Internal shift registers (A — H) L
Output registers (QA — QH) L
(1) For requirements to provide known power-up state, see Section 8.2