SCES212AB April 1999 – April 2014 SN74LVC1G00
The SN74LVC1G00 device contains one 2-input positive-NAND gate and performs the Boolean function
Y = A × B or Y = A + B. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
The DPW package technology is a major breakthrough in IC packaging. Its tiny 0.64 mm square footprint saves significant board space over other package options while still retaining the traditional manufacturing friendly lead pitch of 0.5 mm.