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SN74LVC1G00

ACTIVE

Single 2-input, 1.65-V to 5.5-V NAND gate

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Data sheet

SN74LVC1G00

ACTIVE
Data sheet Order now

Product details

Technology family LVC Number of channels 1 Inputs per channel 1 IOL (max) (mA) 32 IOH (max) (mA) -32 Input type Standard CMOS Output type Push-Pull Features Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns) Data rate (max) (Mbps) 100 Rating Catalog Operating temperature range (°C) -40 to 125
Technology family LVC Number of channels 1 Inputs per channel 1 IOL (max) (mA) 32 IOH (max) (mA) -32 Input type Standard CMOS Output type Push-Pull Features Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns) Data rate (max) (Mbps) 100 Rating Catalog Operating temperature range (°C) -40 to 125
SOT-SC70 (DCK) 5 4.2 mm² (2 mm × 2.1 mm) SOT-5X3 (DRL) 5 2.56 mm² (1.6 mm × 1.6 mm) DSBGA (YZP) 5 2.1875 mm² (— mm × — mm) USON (DRY) 6 1.45 mm² (1.45 mm × 1 mm) X2SON (DPW) 5 0.64 mm² (0.8 mm × 0.8 mm) X2SON (DSF) 6 1 mm² (1 mm × 1 mm) SOT-23 (DBV) 5 8.12 mm² (2.9 mm × 2.8 mm)
  • Available in the Ultra Small 0.64-mm2
    Package (DPW) With 0.5-mm Pitch
  • Supports 5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Provides Down Translation to VCC
  • Max tpd of 3.8 ns at 3.3 V
  • Low Power Consumption, 10-μA Max ICC
  • ±24-mA Output Drive at 3.3 V
  • Ioff Supports Live Insertion, Partial-Power-Down Mode, and Back Drive Protection
  • Latch-Up Performance Exceeds 100 mA
    Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 1000-V Charged-Device Model (C101)
  • Available in the Ultra Small 0.64-mm2
    Package (DPW) With 0.5-mm Pitch
  • Supports 5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Provides Down Translation to VCC
  • Max tpd of 3.8 ns at 3.3 V
  • Low Power Consumption, 10-μA Max ICC
  • ±24-mA Output Drive at 3.3 V
  • Ioff Supports Live Insertion, Partial-Power-Down Mode, and Back Drive Protection
  • Latch-Up Performance Exceeds 100 mA
    Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 1000-V Charged-Device Model (C101)

This single 2-input positive-NAND gate is designed for 1.65-V to 5.5-V VCC operation.

The SN74LVC1G00 performs the Boolean function
Y = A × B or Y = A + B in positive logic.

The CMOS device has high output drive while maintaining low static power dissipation over a broad VCC operating range.

The SN74LVC1G00 is available in a variety of packages, including the ultra-small DPW package with a body size of 0.8 mm × 0.8 mm.

This single 2-input positive-NAND gate is designed for 1.65-V to 5.5-V VCC operation.

The SN74LVC1G00 performs the Boolean function
Y = A × B or Y = A + B in positive logic.

The CMOS device has high output drive while maintaining low static power dissipation over a broad VCC operating range.

The SN74LVC1G00 is available in a variety of packages, including the ultra-small DPW package with a body size of 0.8 mm × 0.8 mm.
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SN74AUP1G00 ACTIVE Single 1-input, 0.8-V to 3.6-V low power NAND gate Voltage range 0.8V to 3.6V, average propagation delay 8ns, average drive strength 4mA
SN74AHC1G00 ACTIVE Single 2-input, 2-V to 5.5-V NAND gate Voltage range 2V to 5.5V, average propagation delay 12ns, average drive strength 9mA

Technical documentation

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Top documentation Type Title Format options Date
* Data sheet SN74LVC1G00 Single 2-Input Positive-NAND Gate datasheet (Rev. AB) PDF | HTML Apr 23, 2014
Application note The Davies Sinusoidal Generator PDF | HTML Oct 31, 2022
Application note Designing and Manufacturing with TI's X2SON Packages Aug 23, 2017

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Package Pins CAD symbols, footprints & 3D models
SOT-SC70 (DCK) 5 Ultra Librarian
SOT-5X3 (DRL) 5 Ultra Librarian
DSBGA (YZP) 5 Ultra Librarian
USON (DRY) 6 Ultra Librarian
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