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Product details

Parameters

Technology Family LVC VCC (Min) (V) 1.65 VCC (Max) (V) 5.5 Channels (#) 1 Inputs per channel 1 IOL (Max) (mA) 32 IOH (Max) (mA) -32 Input type Standard CMOS Output type Push-Pull Features Partial Power Down (Ioff), Over-Voltage Tolerant Inputs, Ultra High Speed (tpd <5ns) Data rate (Max) (Mbps) 100 Rating Catalog Operating temperature range (C) -40 to 125, -40 to 85 open-in-new Find other NAND gate

Package | Pins | Size

DSBGA (YZP) 5 2 mm² .928 x 1.428 SOT-23 (DBV) 5 5 mm² 2.9 x 1.6 SOT-5X3 (DRL) 5 3 mm² 1.6 x 1.6 SOT-SC70 (DCK) 5 4 mm² 2 x 2.1 USON (DRY) 6 1 mm² 1.5 x 1 X2SON (DPW) 5 1 mm² .8 x .8 X2SON (DSF) 6 1 mm² 1 x 1 open-in-new Find other NAND gate

Features

  • Available in the Ultra Small 0.64-mm2
    Package (DPW) With 0.5-mm Pitch
  • Supports 5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Provides Down Translation to VCC
  • Max tpd of 3.8 ns at 3.3 V
  • Low Power Consumption, 10-μA Max ICC
  • ±24-mA Output Drive at 3.3 V
  • Ioff Supports Live Insertion, Partial-Power-Down Mode, and Back Drive Protection
  • Latch-Up Performance Exceeds 100 mA
    Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 1000-V Charged-Device Model (C101)
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Description

This single 2-input positive-NAND gate is designed for 1.65-V to 5.5-V VCC operation.

The SN74LVC1G00 performs the Boolean function
Y = A × B or Y = A + B in positive logic.

The CMOS device has high output drive while maintaining low static power dissipation over a broad VCC operating range.

The SN74LVC1G00 is available in a variety of packages, including the ultra-small DPW package with a body size of 0.8 mm × 0.8 mm.

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Technical documentation

= Top documentation for this product selected by TI
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Type Title Date
* Datasheet SN74LVC1G00 Single 2-Input Positive-NAND Gate datasheet (Rev. AB) Apr. 23, 2014
Technical articles How to keep your motor running safely Jun. 04, 2020
Selection guides Little Logic Guide 2018 (Rev. G) Jul. 06, 2018
Application notes Designing and Manufacturing with TI's X2SON Packages Aug. 23, 2017
Selection guides Logic Guide (Rev. AB) Jun. 12, 2017
Application notes How to Select Little Logic (Rev. A) Jul. 26, 2016
Application notes Implications of Slow or Floating CMOS Inputs (Rev. D) Jun. 23, 2016
Application notes Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
User guides LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
More literature Design Summary for WCSP Little Logic (Rev. B) Nov. 04, 2004
Application notes Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
Application notes Selecting the Right Level Translation Solution (Rev. A) Jun. 22, 2004
Application notes NanoStar™ & NanoFree™ 300μm Solder Bump WCSP Application Feb. 02, 2004
User guides Signal Switch Data Book (Rev. A) Nov. 14, 2003
Application notes Use of the CMOS Unbuffered Inverter in Oscillator Circuits Nov. 06, 2003
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
User guides LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B) Dec. 18, 2002
Application notes Texas Instruments Little Logic Application Report Nov. 01, 2002
Application notes TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
More literature Standard Linear & Logic for PCs, Servers & Motherboards Jun. 13, 2002
Application notes 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) May 22, 2002
Application notes Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices May 10, 2002
More literature STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS Mar. 27, 2002
More literature Military Low Voltage Solutions Apr. 04, 2001
Application notes Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices Dec. 01, 1997
Application notes Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) Aug. 01, 1997
Application notes CMOS Power Consumption and CPD Calculation (Rev. B) Jun. 01, 1997
Application notes LVC Characterization Information Dec. 01, 1996
Application notes Input and Output Characteristics of Digital Integrated Circuits Oct. 01, 1996
Application notes Live Insertion Oct. 01, 1996
User guides Low-Voltage Logic (LVC) Designer's Guide Sep. 01, 1996
Application notes Understanding Advanced Bus-Interface Products Design Guide May 01, 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARDS Download
document-generic User guide
10
Description
Flexible EVM designed to support any device that has a DCK, DCT, DCU, DRL, or DBV package in a 5 to 8 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices

Design tools & simulation

SIMULATION MODELS Download
SCEM165A.ZIP (42 KB) - IBIS Model
SIMULATION MODELS Download
SCEM646.ZIP (7 KB) - PSpice Model

Reference designs

REFERENCE DESIGNS Download
Industrial Communications Gateway PROFINET IRT to PROFIBUS Master Reference Design
TIDEP-0075 — PROFINET is becoming the leading industrial Ethernet protocol in automation due to its high-speed, deterministic communications and enterprise connectivity. However, as the world’s most popular fieldbus, PROFIBUS’s importance and usage will continue for many years due to legacy (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
OPC UA Data Access Server for AM572x Reference Design
TIDEP0078 — OPC UA is an industrial machine-to-machine protocol designed to allow interoperability and communication between all machines connected under Industry 4.0. The TIDEP0078 TI Design demonstrates use of the MatrikonOPC™ OPC UA server development kit (SDK) to allow communications using an OPC UA (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
Single Chip Drive for Industrial Communications and Motor Control
TIDEP0025 This TI design implements a hardware interface solution based on the HEIDENHAIN EnDat 2.2 standard for position or rotary encoders. The platform also allows designers to implement real-time EtherCAT communications standards in a broad range of industrial automation equipment. It enables designers (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
ARM MPU with Integrated BiSS C Master Interface Reference Design
TIDEP0022 Implementation of BiSS C Master protocol on Industrial Communication Sub-System (PRU-ICSS). The design provides full documentation and source code for Programmable Realtime Unit (PRU).
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
ARM MPU with Integrated HIPERFACE DSL Master Interface Reference Design
TIDEP0035 Implementation of HIPERFACE DSL Master protocol on Industrial Communication Sub-System (PRU-ICSS). The two wire interface allows for integration of position feedback wires into motor cable.  Complete solution consists of AM437x PRU-ICSS firmware and TIDA-00177 transceiver reference design.
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
EnDat 2.2 System Reference Design
TIDEP0050 The TIDEP0050 TI Design implements the EnDat 2.2 Master protocol stack and hardware interface solution based on the HEIDENHAIN EnDat 2.2 standard for position or rotary encoders. The design is composed of the EnDat 2.2 Master protocol stack, half-duplex communications using RS485 transceivers and (...)
document-generic Schematic document-generic User guide

CAD/CAE symbols

Package Pins Download
DSBGA (YZP) 5 View options
SC70 (DCK) 5 View options
SON (DRY) 6 View options
SON (DSF) 6 View options
SOT-23 (DBV) 5 View options
SOT-5X3 (DRL) 5 View options
X2SON (DPW) 5 View options

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