SCES470F August   2003  – August 2015 SN74LVC3G17

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Operating Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DCU|8
  • YZP|8
  • DCT|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

9.1 Application Information

The SN74LVC3G17 device contains three buffers and performs the Boolean function Y = A. The device functions as three independent buffers, but because of Schmitt action, it may have different input threshold levels for positive-going (VT+) and negative-going (VT–) signals. In this application, the engineer chooses to use just a single Schmitt Trigger buffer. In this case, the other two inputs should be tied to VCC or GND.

9.2 Typical Application

SN74LVC3G17 sces470_app1.gifFigure 4. Device Power Button Circuit

9.2.1 Design Requirements

This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus contention because it can drive currents that would exceed maximum limits. Outputs can be combined to produce higher drive but the high drive will also create faster edges into light loads so routing and load conditions should be considered to prevent ringing.

9.2.2 Detailed Design Procedure

  1. Recommended Input Conditions:
    • For specified high and low levels, see (VIH and VIL) in Recommended Operating Conditions table.
    • Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC.
  2. Recommend Output Conditions:
    • Load currents should not exceed 50 mA per output and 100 mA total for the part.
    • Series resistors on the output may be used if the user desires to slow the output edge signal or limit the output current.

9.2.3 Application Curves

SN74LVC3G17 graph_15_voh_v_ces794.gifFigure 5. Output Current Drive
vs HIGH-level Output Voltage
SN74LVC3G17 graph_15_vol_v_ces794.gifFigure 6. Output Current Drive
vs LOW-level Output Voltage