SLLSE81A March   2011  – March 2016 SN75LVCP600S

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Equalization
      2. 8.3.2 Auto Low-Power (ALP) Mode (see )
      3. 8.3.3 Out-Of-Band (OOB) Support
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 System Examples
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Community Resources
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

DSK Package
10-Pin (SON)
Top View
SN75LVCP600S po_llse81.gif
TI recommends soldering the package thermal pad to the ground plane for maximum thermal performance.

Pin Functions

PIN I/O TYPE DESCRIPTION
NO. NAME
HIGH SPEED DIFFERENTIAL I/O
3 RX+ I, CML Noninverting and inverting CML differential inputs. These pins are tied to an internal voltage bias by dual termination-resistor circuit.
4 RX– I, CML
8 TX+ O, VML Noninverting and inverting VML differential outputs. These pins are tied to an internal voltage bias by dual termination-resistor circuit.
7 TX– O, VML
CONTROL PINS
5 EQ I, LVCMOS Selects equalization settings per Table 1. Internally tied to GND
9 DE I, LVCMOS Selects de-emphasis settings per Table 1. Internally tied to GND
1 MODE I, LVCMOS Selects SATA or SAS output levels per Table 1. Internally tied to GND
10 SQ_TH I, LVCMOS Selects squelch threshold settings per Table 1. Internally tied to GND
POWER
2 VCC Power Positive supply must be 3.3 V ±10%
6 GND Power Supply ground