SLASF25A January   2022  – January 2025 TAC5111

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements: I2C Interface
    7. 6.7  Switching Characteristics: I2C Interface
    8. 6.8  Timing Requirements: SPI Interface
    9. 6.9  Switching Characteristics: SPI Interface
    10. 6.10 Timing Requirements: TDM, I2S or LJ Interface
    11. 6.11 Switching Characteristics: TDM, I2S or LJ Interface
    12. 6.12 Timing Requirements: PDM Digital Microphone Interface
    13. 6.13 Switching Characteristics: PDM Digital Microphone Interface
    14. 6.14 Timing Diagrams
    15. 6.15 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Serial Interfaces
        1. 7.3.1.1 Control Serial Interfaces
        2. 7.3.1.2 Audio Serial Interfaces
          1. 7.3.1.2.1 Time Division Multiplexed Audio (TDM) Interface
          2. 7.3.1.2.2 Inter IC Sound (I2S) Interface
          3. 7.3.1.2.3 Left-Justified (LJ) Interface
        3. 7.3.1.3 Using Multiple Devices With Shared Buses
      2. 7.3.2  Phase-Locked Loop (PLL) and Clock Generation
      3. 7.3.3  Input Channel Configurations
      4. 7.3.4  Output Channel Configurations
      5. 7.3.5  Reference Voltage
      6. 7.3.6  Programmable Microphone Bias
      7. 7.3.7  Digital PDM Microphone Record Channel
      8. 7.3.8  Incremental ADC (IADC) Mode
      9. 7.3.9  Signal-Chain Processing
        1. 7.3.9.1 ADC Signal-Chain
          1. 7.3.9.1.1  5 to 4 Input Select Multiplexer (5:4 MUX)
          2. 7.3.9.1.2  Programmable Channel Gain and Digital Volume Control
          3. 7.3.9.1.3  Programmable Channel Gain Calibration
          4. 7.3.9.1.4  Programmable Channel Phase Calibration
          5. 7.3.9.1.5  Programmable Digital High-Pass Filter
          6. 7.3.9.1.6  Programmable Digital Biquad Filters
          7. 7.3.9.1.7  Programmable Channel Summer and Digital Mixer
          8. 7.3.9.1.8  Configurable Digital Decimation Filters
            1. 7.3.9.1.8.1 Linear-phase filters
              1. 7.3.9.1.8.1.1 Sampling Rate: 8kHz or 7.35kHz
              2. 7.3.9.1.8.1.2 Sampling Rate: 16kHz or 14.7kHz
              3. 7.3.9.1.8.1.3 Sampling Rate: 24kHz or 22.05kHz
              4. 7.3.9.1.8.1.4 Sampling Rate: 32kHz or 29.4kHz
              5. 7.3.9.1.8.1.5 Sampling Rate: 48kHz or 44.1kHz
              6. 7.3.9.1.8.1.6 Sampling Rate: 96kHz or 88.2kHz
              7. 7.3.9.1.8.1.7 Sampling Rate: 192kHz or 176.4kHz
            2. 7.3.9.1.8.2 Low-latency Filters
              1. 7.3.9.1.8.2.1 Sampling Rate: 24kHz or 22.05kHz
              2. 7.3.9.1.8.2.2 Sampling Rate: 32kHz or 29.4kHz
              3. 7.3.9.1.8.2.3 Sampling Rate: 48kHz or 44.1kHz
              4. 7.3.9.1.8.2.4 Sampling Rate: 96kHz or 88.2kHz
              5. 7.3.9.1.8.2.5 Sampling Rate: 192kHz or 176.4kHz
            3. 7.3.9.1.8.3 Ultra Low-latency Filters
              1. 7.3.9.1.8.3.1 Sampling Rate: 24kHz or 22.05kHz
              2. 7.3.9.1.8.3.2 Sampling Rate: 32kHz or 29.4kHz
              3. 7.3.9.1.8.3.3 Sampling Rate: 48kHz or 44.1kHz
              4. 7.3.9.1.8.3.4 Sampling Rate: 96kHz or 88.2kHz
              5. 7.3.9.1.8.3.5 Sampling Rate: 192kHz or 176.4kHz
          9. 7.3.9.1.9  Automatic Gain Controller (AGC)
          10. 7.3.9.1.10 Voice Activity Detection (VAD)
          11. 7.3.9.1.11 Ultrasonic Activity Detection (UAD)
        2. 7.3.9.2 DAC Signal-Chain
          1. 7.3.9.2.1 Programmable Channel Gain and Digital Volume Control
          2. 7.3.9.2.2 Programmable Channel Gain Calibration
          3. 7.3.9.2.3 Programmable Digital High-Pass Filter
          4. 7.3.9.2.4 Programmable Digital Biquad Filters
          5. 7.3.9.2.5 Programmable Digital Mixer
          6. 7.3.9.2.6 Configurable Digital Interpolation Filters
            1. 7.3.9.2.6.1 Linear-phase filters
              1. 7.3.9.2.6.1.1 Sampling Rate: 8kHz or 7.35kHz
              2. 7.3.9.2.6.1.2 Sampling Rate: 16kHz or 14.7kHz
              3. 7.3.9.2.6.1.3 Sampling Rate: 24kHz or 22.05kHz
              4. 7.3.9.2.6.1.4 Sampling Rate: 32kHz or 29.4kHz
              5. 7.3.9.2.6.1.5 Sampling Rate: 48kHz or 44.1kHz
              6. 7.3.9.2.6.1.6 Sampling Rate: 96kHz or 88.2kHz
              7. 7.3.9.2.6.1.7 Sampling Rate: 192kHz or 176.4kHz
              8. 7.3.9.2.6.1.8 Sampling Rate: 384kHz or 352.8kHz
              9. 7.3.9.2.6.1.9 Sampling Rate 768kHz or 705.6kHz
            2. 7.3.9.2.6.2 Low-latency Filters
              1. 7.3.9.2.6.2.1 Sampling Rate: 24kHz or 22.05kHz
              2. 7.3.9.2.6.2.2 Sampling Rate: 32kHz or 29.4kHz
              3. 7.3.9.2.6.2.3 Sampling Rate: 48kHz or 44.1kHz
              4. 7.3.9.2.6.2.4 Sampling Rate: 96kHz or 88.2kHz
              5. 7.3.9.2.6.2.5 Sampling Rate: 192kHz or 176.4kHz
            3. 7.3.9.2.6.3 Ultra-Low-Latency Filters
              1. 7.3.9.2.6.3.1 Sampling Rate: 24 kHz or 22.05 kHz
              2. 7.3.9.2.6.3.2 Sampling Rate: 32 kHz or 29.4 kHz
              3. 7.3.9.2.6.3.3 Sampling Rate: 48 kHz or 44.1 kHz
              4. 7.3.9.2.6.3.4 Sampling Rate: 96 kHz or 88.2 kHz
              5. 7.3.9.2.6.3.5 Sampling Rate 192 kHz or 176.4 kHz
      10. 7.3.10 Interrupts, Status, and Digital I/O Pin Multiplexing
      11. 7.3.11 Power Tune Mode
    4. 7.4 Device Functional Modes
      1. 7.4.1 Sleep Mode or Software Shutdown
      2. 7.4.2 Active Mode
      3. 7.4.3 Software Reset
    5. 7.5 Programming
      1. 7.5.1 Control Serial Interfaces
        1. 7.5.1.1 I2C Control Interface
          1. 7.5.1.1.1 General I2C Operation
          2. 7.5.1.1.2 I2C Single-Byte and Multiple-Byte Transfers
            1. 7.5.1.1.2.1 I2C Single-Byte Write
            2. 7.5.1.1.2.2 I2C Multiple-Byte Write
            3. 7.5.1.1.2.3 I2C Single-Byte Read
            4. 7.5.1.1.2.4 I2C Multiple-Byte Read
        2. 7.5.1.2 SPI Control Interface
  9. 8 Register Maps
    1. 8.1 Device Configuration Registers
      1. 8.1.1 Book0_Page0 Registers
      2. 8.1.2 B0_P1 Registers
      3. 8.1.3 Book0_Page3 Registers
    2. 8.2 Programmable Coefficient Registers
      1. 8.2.1  Programmable Coefficient Registers: Page 8
      2. 8.2.2  Programmable Coefficient Registers: Page 9
      3. 8.2.3  Programmable Coefficient Registers: Page 10
      4. 8.2.4  Programmable Coefficient Registers: Page 11
      5. 8.2.5  Programmable Coefficient Registers: Page 15
      6. 8.2.6  Programmable Coefficient Registers: Page 16
      7. 8.2.7  Programmable Coefficient Registers: Page 17
      8. 8.2.8  Programmable Coefficient Registers: Page 18
      9. 8.2.9  Programmable Coefficient Registers: Page 19
      10. 8.2.10 Programmable Coefficient Registers: Page 25
      11. 8.2.11 Programmable Coefficient Registers: Page 26
      12. 8.2.12 Programmable Coefficient Registers: Page 27
      13. 8.2.13 Programmable Coefficient Registers: Page 28
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Application
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
      4. 9.2.4 Application Performance Plots
      5. 9.2.5 Example Device Register Configuration Script for EVM Setup
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 AVDD_MODE for 1.8V Operation
      2. 9.3.2 IOVDD_IO_MODE for 1.8V and 1.2V Operation
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.2.8 Programmable Coefficient Registers: Page 18

This register page shown in Table 8-218 consists of the programmable coefficients for the DAC first-order IIR filter, DAC digital volume control for channels 1 to 4 and DAC Beep generator.

Table 8-213 Page 18 Programmable Coefficient Registers
ADDRESS REGISTER RESET DESCRIPTION
0x00 PAGE[7:0] 0x00 Device Page Register
0x08 DAC_IIR_D1_BYT1[7:0] 0x00 Programmable DAC first-order IIR, D1 coefficient byte[31:24]
0x09 DAC_IIR_D1_BYT2[7:0] 0x00 Programmable DAC first-order IIR, D1 coefficient byte[23:16]
0x0A DAC_IIR_D1_BYT3[7:0] 0x00 Programmable DAC first-order IIR, D1 coefficient byte[15:8]
0x0B DAC_IIR_D1_BYT4[7:0] 0x00 Programmable DAC first-order IIR, D1 coefficient byte[7:0]
0x0C DAC_VOL_CH1_BYT1[7:0] 0x00 Digital volume control, DAC channel 1 coefficient byte[31:24]
0x0D DAC_VOL_CH1_BYT2[7:0] 0x80 Digital volume control, DAC channel 1 coefficient byte[23:16]
0x0E DAC_VOL_CH1_BYT3[7:0] 0x00 Digital volume control, DAC channel 1 coefficient byte[15:8]
0x0F DAC_VOL_CH1_BYT4[7:0] 0x00 Digital volume control, DAC channel 1 coefficient byte[7:0]
0x10 DAC_VOL_CH2_BYT1[7:0] 0x00 Digital volume control, DAC channel 2 coefficient byte[31:24]
0x11 DAC_VOL_CH2_BYT2[7:0] 0x80 Digital volume control, DAC channel 2 coefficient byte[23:16]
0x12 DAC_VOL_CH2_BYT3[7:0] 0x00 Digital volume control, DAC channel 2 coefficient byte[15:8]
0x13 DAC_VOL_CH2_BYT4[7:0] 0x00 Digital volume control, DAC channel 2 coefficient byte[7:0]
0x14 DAC_VOL_CH3_BYT1[7:0] 0x00 Digital volume control, DAC channel 3 coefficient byte[31:24]
0x15 DAC_VOL_CH3_BYT2[7:0] 0x80 Digital volume control, DAC channel 3 coefficient byte[23:16]
0x16 DAC_VOL_CH3_BYT3[7:0] 0x00 Digital volume control, DAC channel 3 coefficient byte[15:8]
0x17 DAC_VOL_CH3_BYT4[7:0] 0x00 Digital volume control, DAC channel 3 coefficient byte[7:0]
0x18 DAC_VOL_CH4_BYT1[7:0] 0x00 Digital volume control, DAC channel 4 coefficient byte[31:24]
0x19 DAC_VOL_CH4_BYT2[7:0] 0x80 Digital volume control, DAC channel 4 coefficient byte[23:16]
0x1A DAC_VOL_CH4_BYT3[7:0] 0x00 Digital volume control, DAC channel 4 coefficient byte[15:8]
0x1B DAC_VOL_CH4_BYT4[7:0] 0x00 Digital volume control, DAC channel 4 coefficient byte[7:0]
0x20 DAC_BEEP GEN_SINX_BYT1[7:0] 0x45 Programmable DAC BEEP GEN sin(x) coefficient byte[31:24]
0x21 DAC_BEEP GEN_SINX_BYT2[7:0] 0xF4 Programmable DAC BEEP GEN sin(x) coefficient byte[23:16]
0x22 DAC_BEEP GEN_SINX_BYT3[7:0] 0x61 Programmable DAC BEEP GEN sin(x) coefficient byte[15:8]
0x23 DAC_BEEP GEN_SINX_BYT4[7:0] 0xD0 Programmable DAC BEEP GEN sin(x) coefficient byte[7:0]
0x24 DAC_BEEP GEN_COSX_BYT1[7:0] 0x7F Programmable DAC BEEP GEN cos(x) coefficient byte[31:24]
0x25 DAC_BEEP GEN_COSX_BYT2[7:0] 0xFE Programmable DAC BEEP GEN cos(x) coefficient byte[23:16]
0x26 DAC_BEEP GEN_COSX_BYT3[7:0] 0xFD Programmable DAC BEEP GEN cos(x) coefficient byte[15:8]
0x27 DAC_BEEP GEN_COSX_BYT4[7:0] 0x46 Programmable DAC BEEP GEN cos(x) coefficient byte[7:0]
0x28 DAC_BEEP GEN2_SINX_BYT1[7:0] 0x5D Programmable DAC BEEP GEN2 sin(x) coefficient byte[31:24]
0x29 DAC_BEEP GEN2_SINX_BYT2[7:0] 0xA2 Programmable DAC BEEP GEN2 sin(x) coefficient byte[23:16]
0x2A DAC_BEEP GEN2_SINX_BYT3[7:0] 0x74 Programmable DAC BEEP GEN2 sin(x) coefficient byte[15:8]
0x2B DAC_BEEP GEN2_SINX_BYT4[7:0] 0xB4 Programmable DAC BEEP GEN2 sin(x) coefficient byte[7:0]
0x2C DAC_BEEP GEN2_COSX_BYT1[7:0] 0x01 Programmable DAC BEEP GEN2 cos(x) coefficient byte[31:24]
0x2D DAC_BEEP GEN2_COSX_BYT2[7:0] 0x01 Programmable DAC BEEP GEN2 cos(x) coefficient byte[23:16]
0x2E DAC_BEEP GEN2_COSX_BYT3[7:0] 0x5B Programmable DAC BEEP GEN2 cos(x) coefficient byte[15:8]
0x2F DAC_BEEP GEN2_COSX_BYT4[7:0] 0x4B Programmable DAC BEEP GEN2 cos(x) coefficient byte[7:0]