SLASF33A January   2024  – March 2025 TAC5412-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Timing Requirements: I2C Interface
    7. 5.7  Switching Characteristics: I2C Interface
    8. 5.8  Timing Requirements: SPI
    9. 5.9  Switching Characteristics: SPI
    10. 5.10 Timing Requirements: TDM, I2S or LJ Interface
    11. 5.11 Switching Characteristics: TDM, I2S or LJ Interface
    12. 5.12 Timing Requirements: PDM Digital Microphone Interface
    13. 5.13 Switching Characteristics: PDM Digial Microphone Interface
    14. 5.14 Timing Diagrams
    15. 5.15 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Serial Interfaces
        1. 6.3.1.1 Control Serial Interfaces
        2. 6.3.1.2 Audio Serial Interfaces
          1. 6.3.1.2.1 Time Division Multiplexed Audio (TDM) Interface
          2. 6.3.1.2.2 Inter IC Sound (I2S) Interface
          3. 6.3.1.2.3 Left-Justified (LJ) Interface
        3. 6.3.1.3 Using Multiple Devices With Shared Buses
      2. 6.3.2  Phase-Locked Loop (PLL) and Clock Generation
      3. 6.3.3  Input Channel Configuration
      4. 6.3.4  Reference Voltage
      5. 6.3.5  Microphone Bias
      6. 6.3.6  Digital PDM Microphone Record Channel
      7. 6.3.7  Signal-Chain Processing
        1. 6.3.7.1 ADC Signal-Chain
          1. 6.3.7.1.1  6 to 4 Input Select Multiplexer (6:4 MUX)
          2. 6.3.7.1.2  Programmable Channel Gain and Digital Volume Control
          3. 6.3.7.1.3  Programmable Channel Gain Calibration
          4. 6.3.7.1.4  Programmable Channel Phase Calibration
          5. 6.3.7.1.5  Programmable Digital High-Pass Filter
          6. 6.3.7.1.6  Programmable Digital Biquad Filters
          7. 6.3.7.1.7  Programmable Channel Summer and Digital Mixer
          8. 6.3.7.1.8  Configurable Digital Decimation Filters
            1. 6.3.7.1.8.1 Linear-phase filters
              1. 6.3.7.1.8.1.1 Sampling Rate: 8kHz or 7.35kHz
              2. 6.3.7.1.8.1.2 Sampling Rate: 16kHz or 14.7kHz
              3. 6.3.7.1.8.1.3 Sampling Rate: 24kHz or 22.05kHz
              4. 6.3.7.1.8.1.4 Sampling Rate: 32kHz or 29.4kHz
              5. 6.3.7.1.8.1.5 Sampling Rate: 48kHz or 44.1kHz
              6. 6.3.7.1.8.1.6 Sampling Rate: 96kHz or 88.2kHz
              7. 6.3.7.1.8.1.7 Sampling Rate: 192kHz or 176.4kHz
              8. 6.3.7.1.8.1.8 Sampling Rate: 384kHz or 352.8kHz
              9. 6.3.7.1.8.1.9 Sampling Rate: 768kHz or 705.6kHz
            2. 6.3.7.1.8.2 Low-latency Filters
              1. 6.3.7.1.8.2.1 Sampling Rate: 24kHz or 22.05kHz
              2. 6.3.7.1.8.2.2 Sampling Rate: 32kHz or 29.4kHz
              3. 6.3.7.1.8.2.3 Sampling Rate: 48kHz or 44.1kHz
              4. 6.3.7.1.8.2.4 Sampling Rate: 96kHz or 88.2kHz
              5. 6.3.7.1.8.2.5 Sampling Rate: 192kHz or 176.4kHz
            3. 6.3.7.1.8.3 Ultra-Low-Latency Filters
              1. 6.3.7.1.8.3.1 Sampling Rate: 24kHz or 22.05kHz
              2. 6.3.7.1.8.3.2 Sampling Rate: 32kHz or 29.4kHz
              3. 6.3.7.1.8.3.3 Sampling Rate: 48kHz or 44.1kHz
              4. 6.3.7.1.8.3.4 Sampling Rate: 96kHz or 88.2kHz
              5. 6.3.7.1.8.3.5 Sampling Rate: 192kHz or 176.4kHz
          9. 6.3.7.1.9  Automatic Gain Controller (AGC)
          10. 6.3.7.1.10 Voice Activity Detection (VAD)
          11. 6.3.7.1.11 Ultrasonic Activity Detection (UAD)
        2. 6.3.7.2 DAC Signal-Chain
          1. 6.3.7.2.1 Programmable Channel Gain and Digital Volume Control
          2. 6.3.7.2.2 Programmable Channel Gain Calibration
          3. 6.3.7.2.3 Programmable Digital High-Pass Filter
          4. 6.3.7.2.4 Programmable Digital Biquad Filters
          5. 6.3.7.2.5 Configurable Digital Interpolation Filters
            1. 6.3.7.2.5.1 Linear-phase filters
              1. 6.3.7.2.5.1.1 Sampling Rate: 8kHz or 7.35kHz
              2. 6.3.7.2.5.1.2 Sampling Rate: 16kHz or 14.7kHz
              3. 6.3.7.2.5.1.3 Sampling Rate: 24kHz or 22.05kHz
              4. 6.3.7.2.5.1.4 Sampling Rate: 32kHz or 29.4kHz
              5. 6.3.7.2.5.1.5 Sampling Rate: 48kHz or 44.1kHz
              6. 6.3.7.2.5.1.6 Sampling Rate: 96kHz or 88.2kHz
              7. 6.3.7.2.5.1.7 Sampling Rate: 192kHz or 176.4kHz
              8. 6.3.7.2.5.1.8 Sampling Rate: 384kHz or 352.8kHz
              9. 6.3.7.2.5.1.9 Sampling Rate 768kHz or 705.6kHz
            2. 6.3.7.2.5.2 Low-latency Filters
              1. 6.3.7.2.5.2.1 Sampling Rate: 24kHz or 22.05kHz
              2. 6.3.7.2.5.2.2 Sampling Rate: 32kHz or 29.4kHz
              3. 6.3.7.2.5.2.3 Sampling Rate: 48kHz or 44.1kHz
              4. 6.3.7.2.5.2.4 Sampling Rate: 96kHz or 88.2kHz
              5. 6.3.7.2.5.2.5 Sampling Rate: 192kHz or 176.4kHz
            3. 6.3.7.2.5.3 Ultra-Low-Latency Filters
              1. 6.3.7.2.5.3.1 Sampling Rate: 24kHz or 22.05kHz
              2. 6.3.7.2.5.3.2 Sampling Rate: 32kHz or 29.4kHz
              3. 6.3.7.2.5.3.3 Sampling Rate: 48kHz or 44.1kHz
              4. 6.3.7.2.5.3.4 Sampling Rate: 96kHz or 88.2kHz
              5. 6.3.7.2.5.3.5 Sampling Rate 192kHz or 176.4kHz
          6. 6.3.7.2.6 Programmable Digital Mixer
      8. 6.3.8  Interrupts, Status, and Digital I/O Pin Multiplexing
      9. 6.3.9  Input DC Fault Diagnostics
      10. 6.3.10 Power Tune Mode
    4. 6.4 Device Functional Modes
      1. 6.4.1 Sleep Mode or Software Shutdown
      2. 6.4.2 Active Mode
      3. 6.4.3 Software Reset
    5. 6.5 Programming
      1. 6.5.1 Control Serial Interfaces
        1. 6.5.1.1 I2C Control Interface
          1. 6.5.1.1.1 General I2C Operation
          2. 6.5.1.1.2 I2C Single-Byte and Multiple-Byte Transfers
            1. 6.5.1.1.2.1 I2C Single-Byte Write
            2. 6.5.1.1.2.2 I2C Multiple-Byte Write
            3. 6.5.1.1.2.3 I2C Single-Byte Read
            4. 6.5.1.1.2.4 I2C Multiple-Byte Read
        2. 6.5.1.2 SPI Control Interface
  8. 7 Register Maps
    1. 7.1 Device Configuration Registers
      1. 7.1.1 TAC5412-Q1_B0_P0 Registers
      2. 7.1.2 TAC5412-Q1_B0_P1 Registers
      3. 7.1.3 TAC5412-Q1_B0_P3 Registers
    2. 7.2 Programmable Coefficient Registers
      1. 7.2.1  Programmable Coefficient Registers: Page 8
      2. 7.2.2  Programmable Coefficient Registers: Page 9
      3. 7.2.3  Programmable Coefficient Registers: Page 10
      4. 7.2.4  Programmable Coefficient Registers: Page 11
      5. 7.2.5  Programmable Coefficient Registers: Page 15
      6. 7.2.6  Programmable Coefficient Registers: Page 16
      7. 7.2.7  Programmable Coefficient Registers: Page 17
      8. 7.2.8  Programmable Coefficient Registers: Page 18
      9. 7.2.9  Programmable Coefficient Registers: Page 19
      10. 7.2.10 Programmable Coefficient Registers: Page 25
      11. 7.2.11 Programmable Coefficient Registers: Page 26
      12. 7.2.12 Programmable Coefficient Registers: Page 27
      13. 7.2.13 Programmable Coefficient Registers: Page 28
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Application
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
      4. 8.2.4 Typical Characteristics
      5. 8.2.5 Example Device Register Configuration Script for EVM Setup
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 IOVDD_IO_MODE for 1.8V and 1.2V Operation
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.15 Typical Characteristics

At TA = 25°C, AVDD = 3.3V, IOVDD = 3.3V, BSTVDD = 3.3V, fIN = 1kHz sinusoidal signal, fS = 48kHz, 32-bit audio data, BCLK = 256 × fS, TDM target mode, PLL on, channel gain = 0dB, linear phase decimation/interpolation filters, AC-coupled differential input with VCM = 7.2V, MICBIAS programmed voltage = 8V, 1200Ω/600Ω line-out load in differential/single-ended configuration or 32Ω/16Ω receiver/headphone load as applicable; and other default configurations; measured filter free with an audio precision with a 20Hz to a 20kHz un-weighted bandwidth, unless otherwise noted

TAC5412-Q1 ADC THD+N Level vs Input
AC-coupled differential line input
Figure 5-5 ADC THD+N Level vs Input
TAC5412-Q1 ADC A-weighted DR vs Frequency
AC-coupled differential line input (–­60dBFS)
Figure 5-7 ADC A-weighted DR vs Frequency
TAC5412-Q1 ADC THD+N vs Frequency
AC-coupled differential line input (–1dBFS)
Figure 5-9 ADC THD+N vs Frequency
TAC5412-Q1 ADC Frequency Response
AC-coupled differential line input (–6dBFS)
Figure 5-11 ADC Frequency Response
TAC5412-Q1 ADC FFT with –60dBFS Input
AC-coupled differential line input
Figure 5-13 ADC FFT with –60dBFS Input
TAC5412-Q1 ADC CMRR vs Frequency
DC-coupled differential line input
Figure 5-15 ADC CMRR vs Frequency
TAC5412-Q1 MICBIAS Load Regulation
 AC-coupled differential line input
Figure 5-17 MICBIAS Load Regulation
TAC5412-Q1 DAC THD+N Level vs Input
Differential output
Figure 5-19 DAC THD+N Level vs Input
TAC5412-Q1 DAC THD+N Level vs Input
Pseudo-differential output
Figure 5-21 DAC THD+N Level vs Input
TAC5412-Q1 DAC THD+N Level vs Output Power
Single-ended headphone output, 16Ω load
Figure 5-23 DAC THD+N Level vs Output Power
TAC5412-Q1 DAC THD+N Level vs Frequency
Differential output (–1dBFS input)
Figure 5-25 DAC THD+N Level vs Frequency
TAC5412-Q1 DAC THD+N Level vs Frequency
Differential receiver output, 32Ω load (–1dBFS input)
Figure 5-27 DAC THD+N Level vs Frequency
TAC5412-Q1 DAC FFT with Idle Channel Input
Differential output
Figure 5-29 DAC FFT with Idle Channel Input
TAC5412-Q1 DAC FFT with –1dBFS Input
Differential output
Figure 5-31 DAC FFT with –1dBFS Input
TAC5412-Q1 DAC PSRR vs Frequency
Single-ended output
Figure 5-33 DAC PSRR vs Frequency
TAC5412-Q1 ADC THD+N Level vs Input
AC-coupled single-ended line input
Figure 5-6 ADC THD+N Level vs Input
TAC5412-Q1 ADC A-weighted DR vs Frequency
AC-coupled single-ended line input (–60dBFS)
Figure 5-8 ADC A-weighted DR vs Frequency
TAC5412-Q1 ADC THD+N vs Frequency
AC-coupled single-ended line input (–1dBFS)
Figure 5-10 ADC THD+N vs Frequency
TAC5412-Q1 ADC FFT with Idle Channel Input
AC-coupled differential line input
Figure 5-12 ADC FFT with Idle Channel Input
TAC5412-Q1 ADC FFT with –1dBFS Input
AC-coupled differential line input
Figure 5-14 ADC FFT with –1dBFS Input
TAC5412-Q1 ADC PSRR vs Frequency
AC-coupled differential line input
Figure 5-16 ADC PSRR vs Frequency
TAC5412-Q1 Boost Efficiency vs MICBIAS Load Current
 AC-coupled differential line input
Figure 5-18 Boost Efficiency vs MICBIAS Load Current
TAC5412-Q1 DAC THD+N Level vs Input
Single-ended output
Figure 5-20 DAC THD+N Level vs Input
TAC5412-Q1 DAC THD+N Level vs Output Power
Differential receiver output, 32Ω load
Figure 5-22 DAC THD+N Level vs Output Power
TAC5412-Q1 DAC THD+N Level vs Output Power
Pseudo-differential headphone output, 16Ω load
Figure 5-24 DAC THD+N Level vs Output Power
TAC5412-Q1 DAC THD+N Level vs Frequency
Single-ended output (–1dBFS input)
Figure 5-26 DAC THD+N Level vs Frequency
TAC5412-Q1 DAC THD+N Level vs Frequency
Single-ended headphone output, 16Ω load (–1dBFS input)
Figure 5-28 DAC THD+N Level vs Frequency
TAC5412-Q1 DAC FFT with –60dBFS Input
Differential output
Figure 5-30 DAC FFT with –60dBFS Input
TAC5412-Q1 DAC PSRR vs Frequency
Differential output
Figure 5-32 DAC PSRR vs Frequency
TAC5412-Q1 DAC Frequency Response
Differential output, –6dBFS input with High-pass filter (HPF) disabled
Figure 5-34 DAC Frequency Response