SLASF32 December   2023 TAD5142

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements: TDM, I2S or LJ Interface
    7. 5.7 Switching Characteristics: TDM, I2S or LJ Interface
    8. 5.8 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Hardware Control
      2. 7.3.2 Audio Serial Interfaces
        1. 7.3.2.1 Time Division Multiplexed Audio (TDM) Interface
        2. 7.3.2.2 Inter IC Sound (I2S) Interface
      3. 7.3.3 Phase-Locked Loop (PLL) and Clock Generation
      4. 7.3.4 Analog Output Configurations
      5. 7.3.5 Reference Voltage
      6. 7.3.6 DAC Signal-Chain
        1. 7.3.6.1 Configurable Digital Interpolation Filters
          1. 7.3.6.1.1 Linear Phase Filters
            1. 7.3.6.1.1.1 Sampling Rate: 16 kHz or 14.7 kHz
            2. 7.3.6.1.1.2 Sampling Rate: 24 kHz or 22.05 kHz
            3. 7.3.6.1.1.3 Sampling Rate: 32 kHz or 29.4 kHz
            4. 7.3.6.1.1.4 Sampling Rate: 48 kHz or 44.1 kHz
            5. 7.3.6.1.1.5 Sampling Rate: 96 kHz or 88.2 kHz
            6. 7.3.6.1.1.6 Sampling Rate: 384 kHz or 352.8 kHz
    4. 7.4 Device Functional Modes
      1. 7.4.1 Active Mode
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Application
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
  10. 9 Power Supply Recommendations
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.2 Audio Serial Interfaces

Digital audio data flows between the host processor and the TAD5142 on the digital audio serial interface (ASI), or audio bus. This highly flexible ASI bus includes a TDM mode for multichannel operation, support for the I2S and LJF, and the pin-selectable controller-target configurability for bus clock lines.

The device supports an audio bus controller or target mode of operation using the hardware pin MD0. In target mode, FSYNC and BCLK work as input pins whereas in controller mode, FSYNC and BCLK work as output pins generated by the device. Table 7-1 shows the controller and target mode selection using the MD0 pin.

Table 7-1 Controller and Target Mode Selection
MD0 CONTROLLER AND TARGET SELECTION
Short to Ground Target I2S Mode
Short to Ground with 4.7K Ohms Target TDM Mode
Short to AVDD Controller I2S Mode
Short to AVDD with 4.7K Ohms Controller TDM Mode
Short to AVDD with 22K Ohms Target LJ Mode

The word length for audio serial interface (ASI) in TAD5142 can be selected through MD1 and MD2 Pins in target mode of operation. In controller mode, fixed word length of 32 bits is supported. The TAD5142 also supports 1.8V AVDD operation in target mode with 32 bit word length. Table 7-2 shows the configuration table for setting word length and AVDD supply voltage

Table 7-2 Word Length and Supply Mode Selection
MD1 MD2 CONTROLLER AND TARGET SELECTION
Low Low Word Length=32

AVDD=3.3V
Low High Word Length=32

AVDD=1.8V
High Low Word Length=24

AVDD=3.3V
High High Word Length=16

AVDD=3.3V

The TAD5142 also offers daisy chain option for TDM mode of operation. This option is auto enabled whenever device is selected to be in TDM Mode with MD0. MD6 Pin acts as a Daisy Chain output in this mode. In this case, Device plays the data coming on Slot 0 and Slot 1 and sends the shifted data on remaining slots on MD6.