SLOS903B May   2015  – February 2016 TAS5720L , TAS5720M

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Adjustable I2C Address
      2. 7.3.2 I2C Interface
        1. 7.3.2.1 Writing to the I2C Interface
        2. 7.3.2.2 Reading from the I2C Interface
      3. 7.3.3 Serial Audio Interface (SAIF)
        1. 7.3.3.1 Stereo I2S Format Timing
        2. 7.3.3.2 Stereo Left-Justified Format Timing
        3. 7.3.3.3 Stereo Right-Justified Format Timing
        4. 7.3.3.4 TDM Format Timing
      4. 7.3.4 Audio Signal Path
        1. 7.3.4.1 High-Pass Filter (HPF)
        2. 7.3.4.2 Amplifier Analog Gain and Digital Volume Control
        3. 7.3.4.3 Digital Clipper
        4. 7.3.4.4 Class-D Amplifier Settings
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode (SDZ)
      2. 7.4.2 Sleep Mode
      3. 7.4.3 Active Mode
      4. 7.4.4 Mute Mode
      5. 7.4.5 Faults and Status
    5. 7.5 Register Maps
      1. 7.5.1 Device Identification
      2. 7.5.2 Power Control Register
      3. 7.5.3 Digital Control Register 1
      4. 7.5.4 Digital Control Register 2
      5. 7.5.5 Volume Control Register
      6. 7.5.6 Analog Control Register
      7. 7.5.7 Fault Configuration and Error Status Register
      8. 7.5.8 Digital Clipper 2
      9. 7.5.9 Digital Clipper 1
  8. 8 Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Design Procedure
        1. 8.2.2.1 Overview
        2. 8.2.2.2 Select the PWM Frequency
        3. 8.2.2.3 Select the Amplifier Gain and Digital Volume Control
        4. 8.2.2.4 Select Input Capacitance
        5. 8.2.2.5 Select Decoupling Capacitors
        6. 8.2.2.6 Select Bootstrap Capacitors
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Links
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Applications and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

This section describes a filter-free,TDM application.

8.2 Typical Application

TAS5720L TAS5720M typ_app_slos903.gif Figure 52. Filter Free 3-Wire TDM Application Circuit (I2C_DEV_ID = 0x6C)

8.2.1 Design Requirements

  • Input voltage range PVDD and AVDD: 4.5 V to 26.4 V
  • Input voltage range DVDD: 3.3 V to 3.6 V
  • Input sample rate: 44.1 kHz to 48 kHz or 88.2 kHz to 96 kHz
  • I2C clock frequency: up tp 400 kHz

8.2.2 Design Procedure

8.2.2.1 Overview

The TAS5720L/M is a flexible and easy to use Class D amplifier; therefore the design process is straightforward. Before beginning the design, gather the following information regarding the audio system.

  • PVDD rail planned for the design
  • Speaker or load impedance
  • Audio sample rate
  • Maximum output power requirement
  • Desired PWM frequency

8.2.2.2 Select the PWM Frequency

Set the PWM frequency by writing to the PWM_RATE bits (bits 6-4, reg 0x06). The default setting for this register is 101, which is 16 × LRCLK for single speed applications and 8 × LRCLK for double speed application. This value equates to a default PWM frequency of 768 kHz for a 48 Hz sample rate.

8.2.2.3 Select the Amplifier Gain and Digital Volume Control

To select the amplifier gain setting, the designer must determine the maximum power target and the speaker impedance. Once the parameters have been determined, calculate the required output voltage swing which delivers the maximum output power.

Choose the lowest analog gain setting that corresponds to produce an output voltage swing greater than the required output swing for maximum power. The analog gain can be set by writing to the ANALOG_GAIN bits (bits 3-2, reg 0x06). The default gain setting is 20.7 dBV referenced to 0dBFS input.

8.2.2.4 Select Input Capacitance

Select the bulk capacitors at the PVDD inputs for proper voltage margin and adequate capacitance to support the power requirements. The TAS5720L/M has very good PVDD PSRR, so the  capacitor is more about limiting the ripple and droop for the rest of system than preserving good audio performance. The amount of bulk decoupling can be reduced as long as the droop and ripple is acceptable. One capacitor should be placed near the PVDD inputs at each side of the device. PVDD capacitors should be a low ESR type because they are being used in a high-speed switching application.

8.2.2.5 Select Decoupling Capacitors

Good quality decoupling capacitors should be added at each of the PVDD inputs to provide good reliability, good audio performance, and to meet regulatory requirements. X5R or better ratings should be used in this application. Consider temperature, ripple current, and voltage overshoots when selecting decoupling capacitors. Also, the decoupling capacitors should be located near the PVDD and GND connections to the device to minimize series inductances.

8.2.2.6 Select Bootstrap Capacitors

Each of the outputs require bootstrap capacitors to provide gate drive for the high-side output FETs. For this design, use 0.22-µF, 25-V capacitors of X5R quality or better.

8.2.3 Application Curves

TAS5720L TAS5720M D016_SLOS903.gif
V(PVDD) = 15 V f(PWM) = 384 kHz
Figure 53. THD+N vs. Output Power
TAS5720L TAS5720M D020_SLOS903.gif
V(PVDD) = 24 V f(PWM) = 384 kHz
Figure 54. THD+N vs. Output Power