SLOS903B May   2015  – February 2016 TAS5720L , TAS5720M

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Adjustable I2C Address
      2. 7.3.2 I2C Interface
        1. 7.3.2.1 Writing to the I2C Interface
        2. 7.3.2.2 Reading from the I2C Interface
      3. 7.3.3 Serial Audio Interface (SAIF)
        1. 7.3.3.1 Stereo I2S Format Timing
        2. 7.3.3.2 Stereo Left-Justified Format Timing
        3. 7.3.3.3 Stereo Right-Justified Format Timing
        4. 7.3.3.4 TDM Format Timing
      4. 7.3.4 Audio Signal Path
        1. 7.3.4.1 High-Pass Filter (HPF)
        2. 7.3.4.2 Amplifier Analog Gain and Digital Volume Control
        3. 7.3.4.3 Digital Clipper
        4. 7.3.4.4 Class-D Amplifier Settings
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode (SDZ)
      2. 7.4.2 Sleep Mode
      3. 7.4.3 Active Mode
      4. 7.4.4 Mute Mode
      5. 7.4.5 Faults and Status
    5. 7.5 Register Maps
      1. 7.5.1 Device Identification
      2. 7.5.2 Power Control Register
      3. 7.5.3 Digital Control Register 1
      4. 7.5.4 Digital Control Register 2
      5. 7.5.5 Volume Control Register
      6. 7.5.6 Analog Control Register
      7. 7.5.7 Fault Configuration and Error Status Register
      8. 7.5.8 Digital Clipper 2
      9. 7.5.9 Digital Clipper 1
  8. Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Design Procedure
        1. 8.2.2.1 Overview
        2. 8.2.2.2 Select the PWM Frequency
        3. 8.2.2.3 Select the Amplifier Gain and Digital Volume Control
        4. 8.2.2.4 Select Input Capacitance
        5. 8.2.2.5 Select Decoupling Capacitors
        6. 8.2.2.6 Select Bootstrap Capacitors
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Links
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Detailed Description

7.1 Overview

The TAS5720L/M device is a high-efficiency mono Class-D audio power amplifier optimized for high-transient power capability to utilize the dynamic power headroom of small loudspeakers. It’s capable of delivering more than 15-W continuously into a 4-Ω speaker.

7.2 Functional Block Diagram

TAS5720L TAS5720M fbd_only_slos903.gif

7.3 Feature Description

7.3.1 Adjustable I2C Address

The TAS5720L/M device has two address pins, which allow up to 8 I2C addressable devices to share a common TDM bus. Table 2 lists each I2C Device ID setting.

NOTE

The I2C Device ID is the 7 most significant bits of the 8-bit address transaction on the bus (with the read/write bit being the least significant bit). For example, a Device ID of 0x6C would be read as 0xD8 when the read/write bit is 0.

Table 2. I2C Device Identifier (ID) Generation

ADR1 ADR0 I2C_DEV_ID DEFAULT TDM SLOT
Short to GND Short to GND 0x6C 0
22-kΩ to GND 0x6D 1
22-kΩ to DVDD 0x6E 2
Short to DVDD 0x6F 3
22-kΩ to GND Short to GND 0x70 4
22-kΩ to GND 0x71 5
22-kΩ to DVDD 0x72 6
Short to DVDD 0x73 7

Use a 22-kΩ resistor with a 5% (or better) tolerance to operate as a pull-up or pull-down resistor. By default, the device uses the TDM time slot equal to the offset from the base I2C Device ID (see Table 2). The TDM slot can also be manually configured by setting the TDM_CFG_SRC bit high (bit 6, reg 0x02) and programming the TDM_SLOT_SELECT[2:0] bits to the desired slot (bits 0-2, reg 0x03).

For 2-channel, I2S operation, TDM slots 0 and 1 correspond to right and left channels respectively. For left and right justified formats, TDM slots 0 and 1 correspond to left and right channels respectively.

7.3.2 I2C Interface

The TAS5720L/M device has a bidirectional I2C interface that is compatible with the Inter-Integrated Circuit (I2C) bus protocol and supports both 100-kHz and 400-kHz data transfer rates. This slave-only device does not support a multimaster bus environment or wait-state insertion. The control interface is used to program the registers of the device and to read device status.

The I2C bus employs two signals, SDA (data) and SCL (clock), to communicate between integrated circuits in a system. Data is transferred on the bus serially, one bit at a time. The address and data can be transferred in byte (8-bit) format, with the most-significant bit (MSB) transferred first. In addition, each byte transferred on the bus is acknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with the master device driving a start condition on the bus and ends with the master device driving a stop condition on the bus. The bus uses transitions on the data pin (SDA) while the clock (SCL) is "HIGH" to indicate start and stop conditions. A high-to-low transition on SDA indicates a start and a low-to-high transition indicates a stop. Normal data-bit transitions must occur within the low time of the clock period. The conditions are shown in Figure 39. The master generates the 7-bit slave address and the read/write (R/W) bit to open communication with another device and then waits for an acknowledge condition. The TAS5720L/M device holds SDA "LOW" during the acknowledge clock period to indicate an acknowledgment. When this hold occurs, the master transmits the next byte of the sequence. All compatible devices share the same signals via a bidirectional bus using a wired-AND connection. An external pull-up resistor must be used for the SDA and SCL signals to set the "HIGH" level for the bus.

TAS5720L TAS5720M t0035-01.gif Figure 39. Typical I2C Timing Sequence

Any number of bytes can be transmitted between start and stop conditions. When the last word transfers, the master generates a stop condition to release the bus. A generic data transfer sequence is shown in Figure 39.

7.3.2.1 Writing to the I2C Interface

As shown Figure 40, a single-byte data-write transfer begins with the master device transmitting a start condition followed by the I2C bit and the read/write bit. The read/write bit determines the direction of the data transfer. For a data-write transfer, the read/write bit is a 0. After receiving the correct I2C bit and the read/write bit, the TAS5720L/M device responds with an acknowledge bit. Next, the master transmits the address byte corresponding to the TAS5720L/M device register being accessed. After receiving the address byte, the TAS5720L/M device again responds with an acknowledge bit. Next, the master device transmits the data byte to be written to the memory address being accessed. After receiving the data byte, the TAS5720L/M device again responds with an acknowledge bit. Lastly, the master device transmits a stop condition to complete the single-byte data-write transfer.

TAS5720L TAS5720M t0036-01.gif Figure 40. Single Byte Write Transfer Timing

A multi-byte data write transfer is identical to a single-byte data write transfer except that multiple data bytes are transmitted as shown in Figure 41. After receiving each data byte, the TAS5720L/M device responds with an acknowledge bit. Sequential data bytes are written to sequential addresses.

TAS5720L TAS5720M t0036-02.gif Figure 41. Multi-Byte Write Transfer Timing

7.3.2.2 Reading from the I2C Interface

As shown in Figure 41, a data-read transfer begins with the master device transmitting a start condition, followed by the I2 device address and the read/write bit. For the data read transfer, both a write followed by a read are actually done. Initially, a write is done to transfer the address byte of the internal register to be read. As a result, the read/write bit becomes a 0. After receiving the TAS5720L/M device address and the read/write bit, TAS5720L/M device responds with an acknowledge bit. In addition, after sending the internal memory address byte or bytes, the master device transmits another start condition followed by the TAS5720L/M device address and the read/write bit again. This time, the read/write bit becomes a 1, indicating a read transfer. After receiving the address and the read/write bit, the TAS5720L/M device again responds with an acknowledge bit. Next, the TAS5720L/M device transmits the data byte from the register being read. After receiving the data byte, the master device transmits a not-acknowledge followed by a stop condition to complete the data-read transfer.

TAS5720L TAS5720M t0036-03.gif Figure 42. Single Byte Read Transfer Timing

A multiple-byte data read transfer is identical to a single-byte data read transfer except that multiple data bytes are transmitted by the TAS5720L/M to the master device as shown Figure 43. Except for the last data byte, the master device responds with an acknowledge bit after receiving each data byte.

TAS5720L TAS5720M t0036-04.gif Figure 43. Multi-Byte Read Transfer Timing

7.3.3 Serial Audio Interface (SAIF)

The TAS5720L/M device SAIF supports a variety of standard stereo serial audio formats including I2S, left-justifiedand Right Justified. The device also supports a time division multiplexed (TDM) format that is capable of transporting up to 8 channels of audio data on a single bus. LRCLK and SDIN are sampled on the rising edge of BCLK.

For the stereo formats (I2S, left-justified and right-justified), the TAS5720L/M device supports BCLK to LRCLK ratios of 32, 48 and 64. If the BCLK to LRCLK ratio is 64, MCLK can be tied directly to BCLK. Otherwise MCLK must be driven externally. The valid MCLK to LRCLK ratios are 64, 128, 256 and 512 as long as the frequency of MCLK is 25MHz or less.

For TDM operation, the TAS5720L/M device supports 4 or 8 channels for single speed (44.1/48 kHz) and double speed (88.2/96 kHz) sample rates. Each channel occupies a 32-bit time slot, therefore valid BCLK to LRCLK ratios are 128 and 256. MCLK can be tied to BCLK for all TDM modes or driven externally. If MCLK is driven externally, the MCLK to LRCLK ratio should be 64, 128, 256 or 512 and MCLK should be no faster than 25MHz.

The TAS5720L/M device selects the channel for playback based on either the I2C base address offset or based on a dedicated time slot selection register. See the Adjustable I2C Address section for more information.

7.3.3.1 Stereo I2S Format Timing

Figure 44 illustrates the timing of the stereo I2S format with 64 BCLKs per LRCLK. Two’s complement data is transmitted MSB to LSB with the left channel word beginning one BCLK after the falling edge of LRCLK and the right channel beginning one BCLK after the rising edge of LRCLK. Because data is MSB aligned to the beginning of word transmission, data precision does not be configured. Set the SAIF_FORMAT[2:0] register bits to I2S (register 0x02, bits 2:0=3’b100).

TAS5720L TAS5720M t0034-01_slos903.gif
A. Data presented in two's-complement form with most significant bit (MSB) first.
Figure 44. I2S 64-fSW Format

7.3.3.2 Stereo Left-Justified Format Timing

The stereo left justified format is very similar to the I2S format timing, except the data word begins transmission at the same cycle that LRCLK toggles (when it is shifted by one bit from I2S). The phase of LRCLK is also opposite of I2S. The left channel begins transmission when LRCLK transitions from low to high and the right channel begins transmission when LRCLK transitions from high-to-low. Set the SAIF_FORMAT[2:0] register bits to left-justified (register 0x02, bits 2:0=3’b101).The timing is illustrated in Figure 45.

TAS5720L TAS5720M t0034-02_slos903.gif
A. Data presented in two's-complement form with most significant bit (MSB) first.
Figure 45. Left-Justified 64-fSW Format

7.3.3.3 Stereo Right-Justified Format Timing

The stereo right justified format aligns the LSB of left channel data to the high to low transition of LRCLK and the LSB of the right channel data to the low to high transition of LRCLK. To insure data is received correctly, the SAIF must be configured for the proper data precision. The TAS5720L/M supports 16, 18, 20 and 24-bit data precision in right justified format. Set the SAIF_FORMAT[2:0] register bits (register 0x02, bits 2:0) to the appropriate right-justifiedsetting based on bit precision (value=3’b000 for 24-bit, 3’b001 for 20-bit, 3’b010 for 18-bit and 3’b011 for 16-bit). The timing is illustrated in Figure 46.

TAS5720L TAS5720M t0034-03_slos903.gif Figure 46. Right-Justified 64-fSW Format

7.3.3.4 TDM Format Timing

A TDM frame begins with the low to high transition of LRCLK. As long as LRCLK is high for at least one BCLK period and low for one BCLK period, duty cycle is irrelevent. The SAIF automatically detects the number of time slots as long as valid BCLK to LRCLK ratios are utilized (see Serial Audio Interface (SAIF)).

For I2S aligned TDM operation (when time slot 0 begins one clock cycle after the low to high transition of LRCLK, set SAIF_FORMAT[2:0] register bits to I2S (register 0x02, bits 2:0=3’b100). Data is MSB aligned within the 32-bit time slots, therefore data precision is not required to be configured. The TDM format timing is illustrated in Figure 47.

TAS5720L TAS5720M tdm_i2s_slos903.gif Figure 47. TDM I2S Format

For left-justifiedTDM operation (when time slot 0 begins the cycle LRCLK transitions from low to high), SAIF_FORMAT[2:0] register bits to left-justified(register 0x02, bits 2:0=3’b101). As with I2S, data is MSB aligned. The timing is illustrated in Figure 48.

TAS5720L TAS5720M tdm_lj_slos903.gif Figure 48. TDM Left- and Right-Justified Format

For right-justified TDM operation (when time slot 0 begins the cycle LRCLK transitions from low to high), data is LSB aligned to the 32-bit time slot. As with stereo right-justified formats, the TAS5720L/M must have the data precision configured. Set the SAIF_FORMAT[2:0] register bits (register 0x02, bits 2:0) to the appropriate right-justified setting based on bit precision (value=3’b000 for 24-bit, 3’b001 for 20-bit, 3’b010 for 18-bit and 3’b011 for 16-bit). The timing shown in Figure 48 is the same as left-justified TDM, with the data LSB aligned.

7.3.4 Audio Signal Path

Figure 49 illustrates the audio signal flow from the TDM SAIF to the speaker.

TAS5720L TAS5720M sig_path_slos903.gif Figure 49. Audio Signal Path

7.3.4.1 High-Pass Filter (HPF)

Excessive DC in audio content can damage loudspeakers, therefore the amplifier employs a DC detect circuit that shutdowns the power stage and issue a latching fault if this condition occurs. A high-pass filter is provided in the TAS5720L/M device to remove DC from incoming audio data to prevent this from occurring. Table 3 shows the high-pass, –3 dB corner frequencies for each sample rate. The filter can be bypassed by writing a 1 into bit 7 of register 0x02.

Table 3. High-Pass Filter –3 dB Corner Frequencies by Sample Rate

SAMPLE
RATE (kHZ)
-3dB CORNER
FREQUENCY (Hz)
44.1 3.675
48.0 4.000
88.2 7.350
96.0 8.000

7.3.4.2 Amplifier Analog Gain and Digital Volume Control

The gain from TDM SAIF to speaker is controlled by setting the amplifier’s analog gain and digital volume control. Amplifier analog gain settings are presented as the output level in dBV (dB relative to 1 Vrms) with a full scale serial audio input (0 dBFS) and the digital volume control set to 0 dB. These levels might not be achievable because of analog clipping in the amplifier, therefore they should be used to convey gain only.

Table 4 outlines each gain setting expressed in dBV and VPK.

Table 4. Amplifier Gain Settings

ANALOG_GAIN {1:0}
SETTING
FULL SCALE OUTPUT
dBV VPEAK
00 19.2 12.9
01 20.7 15.3
10 23.5 21.2
11 26.3 29.2

Equation 1 calculates the amplifiers output voltage.

Equation 1. TAS5720L TAS5720M q_vamp_snos852.gif

where

  • VAMP is the amplifier output voltage in dBV
  • Input is the digital input amplitude in dB with respect to 0 dBFS
  • ADVC is the digital volume control setting, –100 dB to 24dB in 0.5-dB steps
  • AAMP is the amplifier analog gain setting (19.2, 20.7, 23.5, or 26.3) in dBV

Clipping in the digital domain occurs if the input level (in dB relative to 0 dBFS) plus the digital volume control setting (in dB) are greater than 0 dB. The signal path has approximately 0.5 dB of headroom, but TI does not recommend utilizing it.

The digital volume control can be adjusted from –100 dB to 24 dB in 0.5-dB steps. Equation 2 calculates the 8-bit volume control register setting at address 0x04.

Equation 2. TAS5720L TAS5720M q_dvcvalue_snos852.gif

For example, digital volume settings of 0 dB, 24 dB and –100 dB map to 0xCF, 0xFF and 0x07 respectively. Values below 0x07 are equivalent to mute (the amplifier continues to switch with no audio).When a change in digital volume control occurs, the device ramps the volume to the new setting in 0.5 dB steps after every 8 audio samples to ensure smooth transitions in volume.

The Class-D amplifier uses a closed-loop architecture, therefore the gain does not depend on the supply input (VPVDD). The approximate threshold for the onset of analog clipping is calculated in Equation 3.

Equation 3. TAS5720L TAS5720M q_vpkmaxpreclip_snos852.gif

where

  • VPK(max,preclip) is the maximum peak unclipped output voltage in V
  • VPVDD is the power supply voltage
  • RL is the speaker load in Ω
  • Rinterconnect is the additional resistance in the PCB (such as cabling and filters) in Ω
  • RDS(on) is the power stage total on resistance (FET+bonding+packaging) in Ω

The effective on-resistance for this device (including FETs, bonding and packaging leads) is approximately 150 mΩ at room temperature and increasex by approximately 1.6 times over 100°C rise in temperature.Table 5 shows approximate maximum unclipped peak output voltages at room temperature (excluding interconnect resistances).

Table 5. Approximate Maximum Unclipped Peak Output Voltage at Room Temperature

SUPPLY VOLTAGE
VPVDD (V)
MAXIMUM UNCLIPPED
PEAK VOLTAGE
VPK (V)
RL = 4 Ω RL = 8 Ω
12 11.16 11.57
17 15.81 16.39

7.3.4.3 Digital Clipper

The digital clipper hard limits the maximum DAC sample value, which provides a simple hardware mechanism to control the largest signal applied to the speaker. Because this block resides in the digital domain, the actual maximum output voltage also depends on the amplifier gain setting and the supply voltage (VPVDD) limited amplifier voltage swing (For example, analog clipping can occur before digital clipping).

The maximum amplifier output voltage (excluding limitation due to swing) is calculated in Equation 4.

Equation 4. TAS5720L TAS5720M q_vampmaxdc_slos852.gif

where

  • VAMP(max,dc) is the amplifier maximum output voltage in dBV
  • DClevel is the digital clipper level
  • AAMP is the amplifier analog gain setting (19.2, 20.7, 23.5, or 26.3) in dBV

Configure the digital clipper by writing the 20-bit DClevel to registers 0x01, 0x10 and 0x11. Set the DClevel to 0xFFFFF effectively bypasses the digital clipper.

7.3.4.4 Class-D Amplifier Settings

The PWM switching rate of the Class-D amplifier is a phase locked multiple of the input audio sample rate. Table 6 lists the PWM switching rate settings as programmed in bit 4 through bit 6 in register 0x06. The double-speed sample rates (for example 88.2kHz, 96kHz) have the same PWM switching frequencies as their equivalent single-speed sample rates.

Table 6. PWM Switching Rates

PWM_RATE[2:0] SINGLE-SPEED
PWM RATE (× fLRCLK)
DOUBLE-SPEED
PWM RATE × fLRCLK)
44.1 kHz, 88.2 kHz
fPWM(kHz)
48 kHz, 96 kHz
fPWM(kHz)
000 6 3 264.6 288
001 8 4 352.8 384
010 10 5 441 480
011 12 6 529.2 576
100 14 7 617.4 672
101 16 8 705.6 768
110 20 10 882 960
111 24 12 1058.4 1152

The Class-D power stage Over Current detector issues a latching fault if the load current exceeds the safe limit for the device. The threshold can be proportionately adjusted if desired by programming bits 4-5 of register 0x08. Table 7 shows the relative setting for each Over Current setting.

Table 7. Over Current Threshold Settings

OC_THRESH
[1:0]
OVERCURRENT
THRESHOLD (%)
00 100
01 75
10 50
11 25

7.4 Device Functional Modes

This section describes the modes of operation for the TAS5720L/M device.

Table 8. Typical Current Consumption(1)

INPUT
VOLTAGE
VPVDD (V)
MODE PWM
FREQUENCY
fPWM (kHz)
IPVDD+IAVDD
(mA)
INPUT
CURRENT
IDVDD (mA)
7.2 Idle and Mute 384 14.5 4.1
768 18.4
Sleep 9.0 1.32
Shutdown 0.039 0.077
12 Idle and Mute 384 17.4 4.1
768 21.3
Sleep 9.0 1.32
Shutdown 0.045 0.077
15 Idle and Mute 384 19.4 4.1
768 22.9
Sleep 9.1 1.32
Shutdown 0.049 0.077
19 Idle and Mute 384 22.4 4.1
768 24.8
Sleep 9.3 1.32
Shutdown 0.054 0.077
24 Idle and Mute 384 26.2 4.1
768 26.9
Sleep 9.4 1.32
Shutdown 0.061 0.077
(1) TA = 25ºC, PVDD pin tied to AVDD pin, VDVDD = 3.3 V, RLOAD = 4Ω, fIN = Idle, fS = 48 kHz, Gain = 20.7 dBV

7.4.1 Shutdown Mode (SDZ)

The device enters shutdown mode if either the SDZ pin is asserted low or the I2C SDZ register bit is set low (bit 0, reg 0x01). In shutdown mode, the device consumes the minimum quiescent current with most analog and digital blocks powered down. The Class-D amplifier power stage powers down and the output pins are in a Hi-Z state. I2C communication remains possible in shutdown mode and register bits states are retained.

If a latching fault condition has occurred (over temperature, Over Current or DC detect), the SDZ pin or I2C bit must toggle low before the fault register can be cleared. For more information on faults and recovery, see the Faults and Status section.

When the device exits shutdown mode (by releasing both the SDZ pin high and setting the I2C SDZ register bit high), the device powers up the internal analog and digital blocks required for operation. If the I2C SLEEP bit is set low (bit 1, reg 0x01), the device powers up the Class-D amplifier and begins the switching of the power stage. If the I2C MUTE bit is set low (bit 4, reg 0x03), the device ramps up the volume to the current setting and begins playing audio.

If shutdown mode is asserted while audio is playing, the device ramps down the volume on the audio, stops the Class-D switching, puts the Class-D power stage output pins in a Hi-Z state and powers down the analog and digital blocks.

7.4.2 Sleep Mode

Sleep mode is similar to shutdown mode, except analog and digital blocks required to begin playing audio quickly are left powered up. Sleep mode operates as a hard mute where the Class-D amplifier stops switching, but the device does not power down completely. Entering sleep mode does not clear latching faults.

7.4.3 Active Mode

If shutdown mode and sleep mode are not asserted, the device is in active mode. During active mode, audio playback is enabled.

7.4.4 Mute Mode

When the I2C_MUTE bit is set high (bit 4, reg 0x03) and the device is in active mode, the volume is ramped down and the Class-D amplifier continues to operate with an idle audio input.

7.4.5 Faults and Status

During the power-up sequence, the power-on-reset circuit (POR) monitoring the DVDD pin domain releases all registers from reset (including the I2C registers) once DVDD is valid. The device does not exit shutdown mode until the PVDD pin has a valid voltage between the undervoltage lockout (UVLO) and overvoltage lockout (OVLO) thresholds. If DVDD drops below the POR threshold the device transitions into shutdown mode with all registers held in reset. If UVLO or OVLO thresholds are violated by the PVDD pin thresholds, the device transitions into shutdown mode, but registers are not be forced into reset. Both of the conditions are non-latching and the device operates normally once supply voltages are valid again. The device can be reset only by reducing DVDD below the POR threshold.

The device transitions into sleep mode if it detects any faults with the SAIF clocks such as

  • Invalid MCLK to LRCLK and BCLK to LRCLK ratios
  • Invalid MCLK and LRCLK switching rates
  • Halting of MCLK, BCLK or LRCLK switching

Upon detection of a SAIF clock error, the device transitions into sleep mode as quickly as possible to limit the possibility of audio artifacts. Once all SAIF clock errors are resolved, the device will volume ramp back to the previous playback state. During a SAIF clock error, the FAULTZ pin will be asserted low and the CLKE bit will be asserted high (register 0x08, bit 3).

While operating in shutdown mode, the SAIF clock error detect circuitry powers down and the CLKE bit reads high. This reading is not an indication of a SAIF clock error. If the device has not entered active mode after a power-up sequence or after transitioning out of shutdown mode, the FAULTZ pin pulses low for only approximately 10 µs every 350 µs. This action prevents a possible locking condition if the FAULTZ is connected to the SDZ pin to accomplish automatic recovery. Once the device has entered active mode one time (after power up or deassertion of shutdown mode), the SAIF clock errors pull the FAULTZ pin low continuously until the fault has cleared.

The device also monitors die temperature, power stage load current and amplifier output DC content and issues latching faults if any of the conditions occur. A die temperature of approximately 150°C causes the device to enter sleep mode and issue an Over-temperature error (OTE) readable via I2C (bit 0, reg 0x08).

Sustained excessive DC content at the output of the Class-D amplifier can damage loudspeakers via voice coil heating. The amplifier has an internal circuit to detect significant DC content that forces the device into sleep mode. The device issues a DC detect error (DCE) readable via I2C (bit 1, reg 0x08).

If the Class-D amplifier load current exceeds the threshold set by the OC_THRESH register bits (bits 5-4, reg 0x08), the device enters sleep mode and issues an Over Current Error (OCE) that is readable via I2C (bit 2, reg 0x08).

During OTE, DCE and OCE, the FAULTZ pin asserts low until the latched fault is cleared. FAULTZ is an open drain pin and requires a pull-up resistor to the DVDD pin.

Latched faults can be cleared only by toggling the SDZ pin or SDZ I2C bit (bit 0, reg 0x01). This toggle does not clear I2C registers (except the fault status of OTE, OCE and DCE). If the device is intended to attempt automatic recovery after latching faults, implement a circuit like the one shown in Figure 50. The device waits approximately 650 ms after a DCE fault has cleared and 1.3 s after an OTE or OCE fault has cleared before releasing FAULTZ high and allowing the device to enter active mode.

TAS5720L TAS5720M auto_recovery_slos903.gif Figure 50. Auto Recovery Circuit

7.5 Register Maps

When writing to registers with reserved bits, maintain the values shown in Table 9 to ensure proper device operation. Default register values are loaded during the power-up sequence or any time the DVDD voltage falls below the power-on-reset (POR) threshold and then returns to valid operation.

Table 9. I2C Register Map Summary

ADDR
(Dec)
ADDR
(Hex)
REGISTER
NAME
REGISTER BITS DEFAULT
(Hex)
B7 B6 B5 B4 B3 B2 B1 B0
0 0x00 Device ID DEVICE_ID 0x01
0 0 0 0 0 0 0 1
1 0x01 Power Control DIGITAL_CLIP_LEVEL [19:14] SLEEP SDZ 0xFD
1 1 1 1 1 1 0 1
2 0x02 Digital Control 1 HPF_BYPASS TDM_CFG_SRC RSV SSZ/DS SAIF_FORMAT 0x04
0 0 0 0 0 1 0 0
3 0x03 Digital Control 2 RSV MUTE RSV TDM_SLOT_SELECT 0x80
1 0 0 0 0 0 0 0
4 0x04 Volume Control VOLUME_CONTROL 0xCF
1 1 0 0 1 1 1 1
6 0x06 Analog Control RSV PWM_RATE ANALOG_GAIN RSV 0x55
0 1 0 1 0 1 0 1
8 0x08 Fault Config and Error Status RSV OC_THRESH CLKE OCE DCE OTE 0x00
0 0 0 0 0 0 0 0
16 0x10 Digital Clipper 2 DIGITAL_CLIP_LEVEL[13:6] 0xFF
1 1 1 1 1 1 1 1
17 0x11 Digital Clipper 1 DIGITAL_CLIP_LEVEL[5:0] RSV 0xFC
1 1 1 1 1 1 0 0

7.5.1 Device Identification

Figure 51. Device Identification, Address: 0x000
7 6 5 4 3 2 1 0
DEVICE_ID
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 10. Device Identification, Address: 0x000

Bit Field Type Reset Description
7 DEVICE_ID[7:0] R 0 This register returns a value of 0x01 when read.
6 0
5 0
4 0
3 0
2 0
1 0
0 1

7.5.2 Power Control Register

Table 1. Power Control Register, Address: 0x001

7 6 5 4 3 2 1 0
DIGITAL_CLIP_LEVEL SLEEP SDZ
R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 11. Power Control Register, Address: 0x001

Bit Field Type Reset Description
7 DIGITAL_CLIP_LEVEL[19:14] R/W 1 This register holds the top 6-bits of the 20-bit Digital Clipper level. The Digital Clipper limits the magnitude of the sample applied to the DAC. See the Digital Clipper section for more information.
6 1
5 1
4 1
3 1
2 1
1 SLEEP R/W 0 When the device enters SLEEP mode, volume ramps down and the Class-D output stage powers down to a Hi-Z state. The rest of the blocks will be kept in a state such that audio playback can be restarted as quickly as possible. This mode has lower dissipation than MUTE, but higher than SHUTDOWN. For more information see the Device Functional Modes section.
0: Exit Sleep (default)
1: Enter Sleep
0 SDZ R/W 1 The device enters SHUTDOWN mode if either this bit is set to a 0 or the SDZ pin is pulled low externally. In SHUTDOWN, the device holds the lowest dissipation state. I2C communication remains functional and all registers are retained. For more information see the Device Functional Modes section.
0: Enter SHUTDOWN
1: Exit SHUTDOWN (default)

7.5.3 Digital Control Register 1

Table 2. Digital Control Register 1, Address: 0x002

7 6 5 4 3 2 1 0
HPF_BYPASS TDM_CFG_SRC RSV SSZ/DS SAIF_FORMAT
R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 12. Digital Control Register 1, Address: 0x002

Bit Field Type Reset Description
7 HPF_BYPASS R/W 0 The high-pass filter removes any DC component in the audio content that could trip the DC detect protection feature in the amplifer, which is a latching fault. Setting this bit bypasses the high-pass filter. See the High-Pass Filter (HPF) section for more information.
0:Enable high-pass filter (default)
1: Bypass high-pass filter
6 TDM_CFG_SRC R/W 0 This bit determines how the device selects which audio channel direct to the playback stream. See the Serial Audio Interface (SAIF) section for more information.
0:Set TDM Channel to I2C Device ID (default).
1:Set TDM Channel to TDM_SLOT_SELECT in register 0x03.
5 RSV[1:0] R/W 0 These bits are reserved and should be set to 00 when writing to this register.
4 R/W 0
3 SSZ/DS R/W 0 This bit sets the sample rate to single speed or double speed operation. See the Serial Audio Interface (SAIF) section for more information.
0: Single speed operation (44.1 kHz/48 kHz) - default.
1: Double speed operation (88.2 kHz/96 kHz)
2 SAIF_FORMAT[2:0] R/W 1 These bits set the Serial Audio Interface format. See the Serial Audio Interface (SAIF) section for more information.
000: Right justified, 24-bit
001: Right justified, 20-bit
1 R/W 0 010: Right justified, 18-bit
011: Right justified, 16-bit
100: I2S (default)
0 R/W 0 101: Left Justified, 16-24 bits
110: Reserved. Do not select this value.
111: Reserved. Do not select this value.

7.5.4 Digital Control Register 2

Table 3. Digital Control Register 2, Address: 0x003

7 6 5 4 3 2 1 0
RSV MUTE RSV TDM_SLOT_SELECT
R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 13. Digital Control Register 2, Address: 0x003

Bit Field Type Reset Description
7 RSV[2:0] R/W 1 These bits are reserved and should be set to 100 when this register is written to
6 R/W 0
5 R/W 0
4 MUTE R/W 0 When set the device ramps down volume and play idle audio. See the Amplifier Analog Gain and Digital Volume Control section for more information.
0: Exit mute mode (default)
1: Enter mute mode
3 RSV R/W 0 This bit is reserved and should be set to 0 when writing to this register.
2 TDM_SLOT_SELECT[2:0] R/W 0 When the TDM_CFG_SRC bit is set to 1 in register 0x02, these bits select which TDM channel is directed to audio playback. See the Serial Audio Interface (SAIF) section for more information
1 R/W 0
0 R/W 0

7.5.5 Volume Control Register

Table 4. Volume Control Register, Address: 0x004

7 6 5 4 3 2 1 0
VOLUME_CONTROL
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 14. Volume Control Register, Address: 0x004

Bit Field Type Reset Description
7 VOLUME_CONTROL[7:0] R/W 1 This register sets the Digital Volume Control, which ranges from -100 dB to +24 dB in 0.5 dB steps. Register settings of less than 0x07 are equivalent to setting the Mute bit in register 0x03. See the Amplifier Analog Gain and Digital Volume Control section for more information.
0xFF: +24.0 dB
6 R/W 1 0xFE: +23.5 dB
5 R/W 0 ...
4 R/W 0 0xCF: 0 dB (default)
3 R/W 1 ...
2 R/W 1 0x08: –99.5 dB
1 R/W 1 0x07: –100 dB
0 R/W 1 < 0x07: MUTE

7.5.6 Analog Control Register

Table 5. Analog Control Register, Address: 0x006

7 6 5 4 3 2 1 0
RSV PWM_RATE ANALOG_GAIN RSV
R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 15. Analog Control Register, Address: 0x006

Bit Field Type Reset Description
7 RSV R/W 0 This bit is reserved and should be set to a 0 when this register is written to.
6 PWM_RATE[2:0] R/W 1 These bits set the PWM switching rate, which is a locked ratio of LRCLK. For more information see the Class-D Amplifier Settings section.
000: 6 × LRCLK (single speed), 3 × LRCLK (double speed)
001: 8 × LRCLK (single speed), 4 × LRCLK (double speed)
5 R/W 0 010: 10 × LRCLK (single speed), 5 × LRCLK (double speed)
011: 12 × LRCLK (single speed), 6 × LRCLK (double speed)
100: 14 × LRCLK (single speed), 7 × LRCLK (double speed)
4 R/W 1 101: 16 × LRCLK (single speed), 8 × LRCLK (double speed) - default
110: 20 × LRCLK (single speed), 10 × LRCLK (double speed)
111: 24 × LRCLK (single speed), 12 × LRCLK (double speed)
3 ANALOG_GAIN[1:0] R/W 0 Sets the analog gain of the Class-D amplifer. The values shown indicate the output level with digital volume control set to 0 dB and a full scale digital input (0 dBFS). This level might not be acheivable because of analog clipping. See the Amplifier Analog Gain and Digital Volume Control section for more information.
00: 19.2 dBV
01: 20.7 dBV (default)
2 R/W 1 10: 23.5 dBV
11: 26.3 dBV
1 RSV[1:0] R/W 0 These bits are reserved and should be set to 01 when writing to this register
0 R/W 1

7.5.7 Fault Configuration and Error Status Register

Table 6. Fault Configuration and Error Status Register, Address: 0x008

7 6 5 4 3 2 1 0
RSV OC_THRESH CLKE OCE DCE OTE
R/W R/W R R R R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 16. Fault Configuration and Error Status Register, Address: 0x008

Bit Field Type Reset Description
7 RSV[1:0] R/W 0 This bit is reserved and should be set to a 00 when this register is written to.
6 R/W 0
5 OC_THRESH[1:0] R/W 0 This register sets the Over Current detector threshold. For more information see the Class-D Amplifier Settings section.
00: 100% of Over Current limit (default)
01: 75% of Over Current limit
4 R/W 1 10: 50% of Over Current limit
11: 25% of Over Current limit
3 CLKE R 0 This bit indicates the status of the SAIF clock error detector. This is a self clearning value.
0: No SAIF clock errors.
1: SAIF clock errors are present.
2 OCE R 0 This bit indicates the status of the over current error detector. This is a latching value
0: The Class-D output stage has not experienced an over current event.
1: The Class-D output stage has experienced an over current event.
1 DCE R 0 This bit indicates the status of the DC detector. This is a latching value.
0: The Class-D output stage has not experienced a DC detect error.
1: The Class-D output stage has experienced a DC detect error.
0 OTE R 0 This bit indicates the status of the over temperature detector. This is a latching value.
0: The Class-D output stage has not experienced an over temperature error.
1: The Class-D output stage has experienced an over temperature error.

7.5.8 Digital Clipper 2

Table 7. Digital Clipper 2, Address: 0x010

7 6 5 4 3 2 1 0
DIGITAL_CLIP_LEVEL
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 17. Digital Clipper 2, Address: 0x010

Bit Field Type Reset Description
7 DIGITAL_CLIP_LEVEL[13:6] R/W 1 This register holds the bits 13 through 6 of the 20-bit Digital Clipper level. The Digital Clipper limits the magnitude of the sample applied to the DAC. See the Digital Clipper section for more information.
6 R/W 1
5 R/W 1
4 R/W 1
3 R/W 1
2 R/W 1
1 R/W 1
0 R/W 1

7.5.9 Digital Clipper 1

Table 8. Digital Clipper 1, Address: 0x011

7 6 5 4 3 2 1 0
DIGITAL_CLIP_LEVEL
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 18. Digital Clipper 1, Address: 0x011

Bit Field Type Reset Description
7 DIGITAL_CLIP_LEVEL[5:0] R/W 1 This register holds the bits 5 through 0 of the 20-bit Digital Clipper level. The Digital Clipper limits the magnitude of the sample applied to the DAC. See the Digital Clipper section for more information.
6 R/W 1
5 R/W 1
4 R/W 1
3 R/W 1
2 R/W 1
1 RSV[1:0] R/W 0 These bits are reserved and should be set to 00 when writing to this register.
0 R/W 0