SLOS946 Data sheet

SLOS946A May 2016 – December 2016 TAS5722L

PRODUCTION DATA.

Package Options

Mechanical Data (Package|Pins)

RSM|32
- MPQF195B

Thermal pad, mechanical data (Package|Pins)

RSM|32
- QFND112H

Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

			MIN	MAX	UNIT
V_CC	Supply voltage⁽²⁾	PVDD, AVDD	–0.3	20	V
V_CC	Supply voltage⁽²⁾	DVDD	–0.3	2.25	V
	Digital input voltage	Digital inputs referenced to DVDD supply	–0.5	V_DVDD + 0.5	V
T_A	Ambient operating temperature		–25	85	°C
T_stg	Storage temperature range		–40	125	°C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods my affect device reliability.

(2) All voltages are with respect to network ground pin.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾	±2000	V
V_(ESD)	Electrostatic discharge	Charged device model (CDM), per JEDEC specification JESD22-C101, all pins⁽²⁾	±750	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

		MIN	TYP	MAX	UNIT
PVDD AVDD	Power supply voltage	4.5		17	V
DVDD	Power supply voltage	1.65	1.8	2	V
V_IH(DR)	High-level digital input voltage		V_DVDD		V
V_IL(DR)	Low-level digital input voltage		0		V
R_SPK	Minimum speaker load	3.2			Ω
T_A	Operating free-air temperature	–25		85	°C
T_J	Operating junction temperature	–25		150	°C

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		TAS5722L	UNIT
		RSM (QFN)
		32 PINS
R_θJA	Junction-to-ambient thermal resistance⁽²⁾	37.3	°C/W
R_θJCtop	Junction-to-case (top) thermal resistance⁽³⁾	30.4
R_θJB	Junction-to-board thermal resistance⁽⁴⁾	7.9
ψ_JT	Junction-to-top characterization parameter⁽⁵⁾	0.4
ψ_JB	Junction-to-board characterization parameter⁽⁶⁾	7.7
R_θJCbot	Junction-to-case (bottom) thermal resistance⁽⁷⁾	2.5

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report (SPRA953).

(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a.

(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8.

(5) The junction-to-top characterization parameter, ψ_JT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining R_θJA, using a procedure described in JESD51-2a (sections 6 and 7).

(6) The junction-to-board characterization parameter, ψ_JB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining R_θJA, using a procedure described in JESD51-2a (sections 6 and 7).

(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

6.5 Electrical Characteristics

V_PVDD = 16.5 V, V_DVDD = 1.8 V, R_L = 4 Ω + 33 µH, f_PWM = 576 kHz, 22-Hz to 20- kHz Bandwidth, AP AUX-0025 + AES17 Filter (unless otherwise noted)

PARAMETER		CONDITIONS	MIN	TYP	MAX	UNIT
DIGITAL INPUT AND OUTPUT
V_IH	High-level digital input logic voltage threshold	All digital pins	70%
V_IL	Low-level digital input logic voltage threshold	All digital pins			30%
I_IH	Input logic "high" leakage for digital inputs	All digital pins, excluding SDZ			15	µA
I_IL	Input logic "low" leakage for digital inputs	All digital pins, excluding SDZ			–15	µA
I_IH(SDZ)	Input logic "high" leakage for SDZ inputs	SDZ			1	µA
I_IL(SDZ)	Input logic "low" leakage for SDZ inputs	SDZ			–1	µA
V_OL	Output logic "low" for FAULTZ open drain Output	I_OL = –2 mA			10% V_DVDD
C_IN	Input capacitance for digital inputs	All digital pins		5		pF
MASTER CLOCK
D_MCLK	Allowable MCLK duty cycle		45%	50%	55%
f_MCLK	MCLK input frequency				25	MHz
	Supported single-speed MCLK frequencies	values: 64, 128, 256 and 512	2.8		24.6	MHz
	Supported double-speed MCLK frequencies	values: 64, 128 and 256	5.6		24.6	MHz
SERIAL AUDIO PORT
D_BCLK	Allowable BCLK duty cycle		45%	50%	55%
f_BCLK	BCLK input frequency				25	MHz
	Supported single-speed BCLK frequencies	values: 64, 96, 128, 192 and 256	2.8		12.3	MHz
	Supported double-speed BCLK frequencies	values: 64, 96, 128, 192 and 256	5.6		24.6	MHz
f_S	Supported single-speed input sample rates	values: 44.1 and 48	44.1		48	kHz
f_S	Supported double-speed input sample rates	values: 88.2 and 96	88.2		96	kHz
I²C CONTROL PORT
C_L(I2C)	Allowable load capacitance for each I²C Line				400	pF
f_SCL	SCL frequency	No wait states			400	kHz
PROTECTION
OTE_THRESH	Over-temperature error (OTE) threshold			150		°C
OTE_HYST	Over-temperature error (OTE) hysteresis			15		°C
OCE_THRESH	overcurrent error (OCE) threshold	V_PVDD = 16.5 V, T_A = 25°C		5		A
DCE_THRESH	DC error (DCE) threshold	V_PVDD = 16.5V, TA = 25°C		2.6		V
AMPLIFIER PERFORMANCE
P_OUT	Continuous average power	R_L = 8 Ω+33 µH, 1% THD+N, V_PVDD = 12 V, f_IN = 1 kHz		8.2		W
		R_L = 8 Ω+33 µH, 1% THD+N, V_PVDD = 16.5 V, f_IN = 1 kHz		15.25
		R_L = 4 Ω+33 µH, 1% THD+N, V_PVDD = 12 V, f_IN = 1 kHz		14.25
		R_L = 4 Ω+33 µH, 1% THD+N, V_PVDD = 16.5 V, f_IN = 1 kHz		16
THD+N	Total harmonic distortion plus noise	R_L = 8 Ω+33 µH, V_PVDD = 12 V, P_OUT = 4.25 W, 20 Hz ≤ f_IN≤ 20 kHz		0.05%
		R_L = 8 Ω+33 µH, V_PVDD = 16.5 V, P_OUT = 4.25 W, 20 Hz ≤ f_IN≤ 20 kHz		0.05%
		R_L = 4 Ω+33 µH, V_PVDD = 12 V, P_OUT = 8.25 W, 20 Hz ≤ f_IN≤ 20 kHz		0.05%
		R_L = 4 Ω+33 µH, V_PVDD = 16.5 V, P_OUT = 8.25 W, 20 Hz ≤ f_IN≤ 20 kHz		0.06%
P_EFF	Power efficiency	R_L = 8 Ω+33 µH, V_PVDD = 16.5 V, P_OUT = 10 W		90%
P_EFF	Power efficiency	R_L = 4 Ω+33 µH, V_PVDD = 16.5 V, P_OUT = 14 W		87%
V_N	Integrated noise floor voltage	A-Weighted, Gain = 20.7dBV, R_L = 8 Ω+33 µH		50		µVrms
KCP	Click-pop performance	Into and out of HW reset, into and out of SW shutdown, when SAIF clocks are applied or removed and during power rail cycling. Measured using Maxim click-pop measurement method.		-60		dB
φ _CC	Channel-to-channel phase shift	Output phase shift between multiple devices from 20 Hz to 20 kHz. Across all sample frequencies and SAIF operating modes.		0.2		deg
PSRR	Power supply rejection ratio	AC, 5.5 V ≤ V_PVDD ≤ 16.5 V, DVDD = 1.8 V+200 mV_P-P, f_RIPPLE from 20 Hz to 20 kHz		69		dB
		AC, V_PVDD = 16.5 V+200 mV_P-P, f_RIPPLE from 20 Hz to 5 kHz		64
		AC, V_PVDD = 16.5 V+100 mV_P-P, f_RIPPLE from 5 kHz to 20 kHz		60
AV₀₀	Amplifier analog gain⁽¹⁾	ANALOG_GAIN[1:0] register bits set to "00"		19.2		dBV
AV₀₁		ANALOG_GAIN[1:0] register bits set to "01"		20.7		dBV
AV₁₀		ANALOG_GAIN[1:0] register bits set to "10"		23.5		dBV
AV₁₁		ANALOG_GAIN[1:0] register bits set to "11"		26.3		dBV
AV_ERROR	Amplifier analog gain error				±0.15	dB
V_OS	DC output offset voltage	Measured between OUTP and OUTN		1.5		mV
A_RIPPLE	Frequency response	Maximum deviation above or below passband gain.		±0.15		dB
f_LP	-3 dB Output Cutoff Frequency			0.47×f_S		Hz
R_DS(on)FET	Power stage FET on-resistance	T_A = 25°C		120		mΩ
R_DS(on)TOT	Power stage total on-resistance (FET+bond+package)	T_A = 25°C		150		mΩ
I_P-P	Peak output current	T_A = 25°C		5		A
f_PWM	PWM switching frequency	values: 6, 8, 10, 12, 14, 16, 20 and 24	6		24	MHz

(1) When PVDD is less than 5.5 V, the voltage regulator that operates the analog circuitry does not have enough headroom to maintain the nominal 5.4-V internal voltage. The lack of headroom causes a direct reduction in gain (approximately –0.8 dB at 5 V and –1.74 dB at 4.5 V), but the device functions properly down to V_PVDD = 4.5 V. For operation below 5.5V, the VREG_LVL bit (register 0x14, bit 2) can be set high, which reduces the internal voltage regulator output voltage to prevent variation in gain. When the bit is set high, all gain settings are reduced by 3dB.

6.6 Timing Requirements

			MIN	NOM	MAX	UNIT
t_ACTIVE	Shutdown to Active Time	From deassertion of SDZ (both pin and I²C register bit) until the Class-D amplifier begins switching.		25		ms
t_WAKE	Wake Time	From the deassertion of SLEEP until the Class-D amplifier starts switching.		1		ms
t_SLEEP	Sleep Time	From the assertion of SLEEP until the Class-D amplifier stops switching.		t_vrmp+1		ms
t_MUTE	Play to Mute Time	From the assertion of MUTE until the volume has ramped to the minimum.		t_vrmp		ms
t_PLAY	Un-Mute to Play Time	From the deassertion of MUTE until the volume has returned to its current setting.		t_vrmp		ms
t_SD	Active to Shutdown Time	From the assertion of SDZ (pin or I²C register bit) until the Class-D amplifier stops switching.		t_vrmp+1		ms
SERIAL AUDIO PORT
t_{H_L}	Time High/Low, BCLK, LRCLK, SDI inputs		10			ns
t_SU / t_HLD	Setup and hold time. LRCLK, SDI input to BCLK edge.	Input t_RISE ≤ 1 ns, input t_FALL ≤ 1 ns	5			ns
		Input t_RISE ≤ 4 ns, input t_FALL ≤ 4ns	8
		Input t_RISE ≤ 8 ns, input t_FALL ≤ 8ns	12
t_RISE	Rise-time BCLK, LRCLK, SDI inputs				8	ns
t_FALL	Fall-time BCLK, LRCLK, SDI inputs				8	ns
I²C CONTROL PORT
t_BUF	Bus free time between start and stop conditions		1.3			µs
t_H1(I2C)	Hold Time, SCL to SDA		0			ns
t_H2(I2C)	Hold Time, start condition to SCL		0.6			µs
t_START(I2C)	I2C Startup Time after DVDD Power On Reset				12	ms
t_R(I2C)	Rise Time, SCL and SDA				300	ns
t_F(I2C)	Fall Time, SCL and SDA				300	ns
t_SU1(I2C)	Setup, SDA to SCL		100			ns
t_SU2(I2C)	Setup, SCL to start condition		0.6			µs
t_SU3(I2C)	Setup, SCL to stop condition		0.6			µs
t_W(H)	Required pulse duration, SCL "HIGH"		0.6			µs
t_W(L)	Required pulse duration, SCL "LOW"		1.3			µs
PROTECTION
t_FAULTZ	Amplifier fault time-out period	DC detect error		650		ms
t_FAULTZ	Amplifier fault time-out period	OTE or OCE fault		1.3		s

Figure 1. SAIF Timing

Figure 2. SCL and SDA Timing

Figure 3. Start and Stop Conditions Timing

Figure 4. Mode Timing

6.7 Typical Characteristics

T_A = 25ºC, V_DVDD = 1.8 V, f_IN = 1 kHz, f_PWM 768 kHz, f_s = 48 kHz, Gain = 20.7 dBV, SDZ = 1, Measured using TAS5722LEVM with an Audio Precision SYS-2722 and AUX-0025 filter with 22-Hz-to-20- kHz un-weighted bandwidth using the 20- kHz pre-analyzer filter + 20- kHz brick-wall filter (unless otherwise specified). 33 µH inductors were added in series with 4 Ω loads and 68 µH inductors were placed in series with 8 Ω loads due to the ferrite bead filters.