SCPS192E April   2009  – January 2023 TCA6408A

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Interface Timing Requirements
    7. 6.7 Reset Timing Requirements
    8. 6.8 Switching Characteristics
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 Voltage Translation
      2. 8.3.2 I/O Port
      3. 8.3.3 Interrupt Output ( INT)
      4. 8.3.4 Reset Input ( RESET)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-On Reset (POR)
      2. 8.4.2 Powered-Up
    5. 8.5 Programming
      1. 8.5.1 I2C Interface
      2. 8.5.2 Bus Transactions
        1. 8.5.2.1 Writes
        2. 8.5.2.2 Reads
    6. 8.6 Register Map
      1. 8.6.1 Device Address
      2. 8.6.2 Control Register and Command Byte
      3. 8.6.3 Register Descriptions
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Minimizing ICC When I/O is Used to Control LEDs
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power-On Reset Requirements
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
      1.      Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10.1 Power-On Reset Requirements

In the event of a glitch or data corruption, TCA6408A can be reset to its default conditions by using the power-on reset feature. Power-on reset requires that the device go through a power cycle to be completely reset. This reset also happens when the device is powered on for the first time in an application.

Ramping up the device VCCP before VCCI is recommended to prevent SDA from potentially being stuck LOW.

The two types of power-on reset are shown in Figure 10-1 and Figure 10-2.

GUID-A5FC7971-04A0-4C12-A04B-0B253E172A78-low.gifFigure 10-1 VCC is Lowered Below 0.2 V Or 0 V and then Ramped Up to VCC
GUID-1B2A81CF-0C29-4D8C-96D3-4173EF05BE72-low.gifFigure 10-2 VCC is Lowered Below the POR Threshold, then Ramped Back Up to VCC

Table 10-1 specifies the performance of the power-on reset feature for TCA6408A for both types of power-on reset.

Table 10-1 Recommended Supply Sequencing and Ramp Rates at TA = 25°C(1)
PARAMETERMINTYPMAXUNIT
tFTFall rateSee Figure 10-10.12000ms
tRTRise rateSee Figure 10-10.12000ms
tRR_GNDTime to re-ramp (when VCC drops to GND)See Figure 10-11μs
tRR_POR50Time to re-ramp (when VCC drops to VPOR_MIN – 50 mV)See Figure 10-21μs
VCC_GHLevel that VCCP can glitch down to, but not cause a functional disruption when VCCX_GW = 1 μsSee Figure 10-31.2V
tGWGlitch width that will not cause a functional disruption when VCCX_GH = 0.5 × VCCxSee Figure 10-310μs
VPORFVoltage trip point of POR on falling VCC0.7V
VPORRVoltage trip point of POR on rising VCC1.4V
(1) Not tested. Specified by design.

Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width (tGW) and height (tGH) are dependent on each other. The bypass capacitance, source impedance, and device impedance are factors that affect power-on reset performance. Figure 10-3 and Table 10-1 provide more information on how to measure these specifications.

GUID-56BF0F05-C241-4022-9CFC-A190032F1706-low.gifFigure 10-3 Glitch Width And Glitch Height

VPOR is critical to the power-on reset. VPOR is the voltage level at which the reset condition is released and all the registers and the I2C/SMBus state machine are initialized to the default states. The value of VPOR differs based on the VCC being lowered to or from 0. Figure 10-4 and Table 10-1 provide more details on this specification.

GUID-88EDA7EF-1319-4598-8B76-88C59AEC05A0-low.gifFigure 10-4 VPOR