SCPS222C May   2010  – October 2015 TCA8418E


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  I2C Interface Timing Requirements
    7. 6.7  Reset Timing Requirements for Standard Mode, Fast Mode, Fast Mode Plus (FM+) I2C Bus
    8. 6.8  Switching Characteristics for Standard Mode, Fast Mode, Fast Mode Plus (FM+) I2C Bus
    9. 6.9  Keypad Switching Characteristics for Standard Mode, Fast Mode, Fast Mode Plus (FM+) I2C Bus
    10. 6.10 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Key Events
        1. Key Event Table
        2. General Purpose Input (GPI) Events
        3. Key Event (FIFO) Reading
        4. Key Event Overflow
      2. 8.3.2 Keypad Lock/Unlock
      3. 8.3.3 Keypad Lock Interrupt Mask Timer
      4. 8.3.4 Control-Alt-Delete Support
      5. 8.3.5 Interrupt Output
        1. 50-µs Interrupt Configuration
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-On Reset (POR)
      2. 8.4.2 Powered (Key Scan Mode)
        1. Idle Key Scan Mode
        2. Active Key Scan Mode
    5. 8.5 Programming
      1. 8.5.1 I2C Interface
      2. 8.5.2 Bus Transactions
        1. Writes
        2. Reads
    6. 8.6 Register Maps
      1. 8.6.1 Device Address
      2. 8.6.2 Control Register and Command Byte
        1.  Configuration Register (Address 0x01)
        2.  Interrupt Status Register, INT_STAT (Address 0x02)
        3.  Key Lock and Event Counter Register, KEY_LCK_EC (Address 0x03)
        4.  Key Event Registers (FIFO), KEY_EVENT_A-J (Address 0x04-0x0D)
        5.  Keypad Lock1 to Lock2 Timer Register, KP_LCK_TIMER (Address 0x0E)
        6.  Unlock1 and Unlock2 Registers, UNLOCK1/2 (Address 0x0F-0x10)
        7.  GPIO Interrupt Status Registers, GPIO_INT_STAT1-3 (Address 0x11-0x13)
        8.  GPIO Data Status Registers, GPIO_DAT_STAT1-3 (Address 0x14-0x16)
        9.  GPIO Data Out Registers, GPIO_DAT_OUT1-3 (Address 0x17-0x19)
        10. GPIO Interrupt Enable Registers, GPIO_INT_EN1-3 (Address 0x1A-0x1C)
        11. Keypad or GPIO Selection Registers, KP_GPIO1-3 (Address 0x1D-0x1F)
        12. GPI Event Mode Registers, GPI_EM1-3 (Address 0x20-0x22)
        13. GPIO Data Direction Registers, GPIO_DIR1-3 (Address 0x23-0x25)
        14. GPIO Edge/Level Detect Registers, GPIO_INT_LVL1-3 (Address 0x26-0x28)
        15. Debounce Disable Registers, DEBOUNCE_DIS1-3 (Address 0x29-0x2B)
        16. GPIO Pullup Disable Register, GPIO_PULL1-3 (Address 0x2C-0x2E)
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Ghosting Considerations
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. Designing the Hardware Layout
        2. Configuring the Registers
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Community Resources
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Power Supply Recommendations

In the event of a glitch or data corruption, TCA8418E can be reset to its default conditions by using the power-on reset feature. Power-on reset requires that the device go through a power cycle to be completely reset. This reset also happens when the device is powered on for the first time in an application.

The two types of power-on reset are shown in Figure 36 and Figure 37.

TCA8418E pwronrstreq01_cps181.gif Figure 36. VCC is Lowered Below 0.2 V or 0 V and Then Ramped Up to VCC
TCA8418E pwronrstreq02_cps181.gif Figure 37. VCC is Lowered Below the POR Threshold, Then Ramped Back Up to VCC

Table 28 specifies the performance of the power-on reset feature for TCA8418E for both types of power-on reset.

Table 28. Recommended Supply Sequencing and Ramp Rates(1)

VCC_FT Fall rate See Figure 36 1 100 ms
VCC_RT Rise rate See Figure 36 0.01 100 ms
VCC_TRR_GND Time to re-ramp (when VCC drops to GND) See Figure 36 0.001 ms
VCC_TRR_POR50 Time to re-ramp (when VCC drops to VPOR_MIN – 50 mV) See Figure 37 0.001 ms
VCC_GH Level that VCCP can glitch down to, but not cause a functional disruption when VCCX_GW = 1 μs See Figure 38 1.2 V
VCC_GW Glitch width that will not cause a functional disruption when VCCX_GH = 0.5 × VCCx See Figure 38 10 μs
VPORF Voltage trip point of POR on falling VCC 0.76 1.15 V
VPORR Voltage trip point of POR on rising VCC 1.03 1.43 V
(1) TA = –40°C to 85°C (unless otherwise noted)

Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width (VCC_GW) and height (VCC_GH) are dependent on each other. The bypass capacitance, source impedance, and device impedance are factors that affect power-on reset performance. Figure 38 and Table 28 provide more information on how to measure these specifications.

TCA8418E pwronrstreq03_cps181.gif Figure 38. Glitch Width and Glitch Height

VPOR is critical to the power-on reset. VPOR is the voltage level at which the reset condition is released and all the registers and the I2C/SMBus state machine are initialized to their default states. The value of VPOR differs based on the VCC being lowered to or from 0. Figure 39 and Table 28 provide more details on this specification.

TCA8418E pwronrstreq04_cps181.gif Figure 39. VPOR

For proper operation of the power-on reset feature, use as directed in the previous figures and table above.