SCPS222C May 2010 – October 2015 TCA8418E
In the event of a glitch or data corruption, TCA8418E can be reset to its default conditions by using the power-on reset feature. Power-on reset requires that the device go through a power cycle to be completely reset. This reset also happens when the device is powered on for the first time in an application.
Table 28 specifies the performance of the power-on reset feature for TCA8418E for both types of power-on reset.
|VCC_FT||Fall rate||See Figure 36||1||100||ms|
|VCC_RT||Rise rate||See Figure 36||0.01||100||ms|
|VCC_TRR_GND||Time to re-ramp (when VCC drops to GND)||See Figure 36||0.001||ms|
|VCC_TRR_POR50||Time to re-ramp (when VCC drops to VPOR_MIN – 50 mV)||See Figure 37||0.001||ms|
|VCC_GH||Level that VCCP can glitch down to, but not cause a functional disruption when VCCX_GW = 1 μs||See Figure 38||1.2||V|
|VCC_GW||Glitch width that will not cause a functional disruption when VCCX_GH = 0.5 × VCCx||See Figure 38||10||μs|
|VPORF||Voltage trip point of POR on falling VCC||0.76||1.15||V|
|VPORR||Voltage trip point of POR on rising VCC||1.03||1.43||V|
Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width (VCC_GW) and height (VCC_GH) are dependent on each other. The bypass capacitance, source impedance, and device impedance are factors that affect power-on reset performance. Figure 38 and Table 28 provide more information on how to measure these specifications.
VPOR is critical to the power-on reset. VPOR is the voltage level at which the reset condition is released and all the registers and the I2C/SMBus state machine are initialized to their default states. The value of VPOR differs based on the VCC being lowered to or from 0. Figure 39 and Table 28 provide more details on this specification.
For proper operation of the power-on reset feature, use as directed in the previous figures and table above.