SCPS222C Data sheet

SCPS222C May 2010 – October 2015 TCA8418E

PRODUCTION DATA.

Package Options

Mechanical Data (Package|Pins)

YFP|25
- MXBG084M

Thermal pad, mechanical data (Package|Pins)

Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings⁽¹⁾

over operating free-air temperature range (unless otherwise noted)

				MIN	MAX	UNIT
V_CC	Supply voltage			–0.5	4.6	V
V_I	Input voltage ⁽²⁾			–0.5	4.6	V
V_O	Voltage range applied to any output in the high-impedance or power-off state⁽²⁾			–0.5	4.6	V
V_O	Output voltage in the high or low state⁽²⁾			–0.5	4.6	V
I_IK	Input clamp current	V_I < 0			±20	mA
I_OK	Output clamp current	V_O < 0			±20	mA
I_OL	Continuous output Low current	P port, SDA	V_O = 0 to V_CC		50	mA
I_OL	Continuous output Low current	INT	V_O = 0 to V_CC		25
I_OH	Continuous output High current	P port	V_O = 0 to V_CC		50
T_stg	Storage temperature			–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (Non-GPIO pins)⁽¹⁾	±2000	V
		Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±1000
		Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (GPIO pins)⁽¹⁾	±15000

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

			MIN	MAX	UNIT
V_CC	Supply voltage		1.65	3.6	V
V_IH	High-level input voltage	SCL, SDA, ROW0–7, COL0–9, RESET	0.7 × V_CC	3.6	V
V_IL	Low-level input voltage	SCL, SDA, ROW0–7, COL0–9, RESET	–0.5	0.3 × V_CC	V
I_OH	High-level output current	ROW0–7, COL0–9		10	mA
I_OL	Low-level output current	ROW0–7, COL0–9		25	mA
T_A	Operating free-air temperature		–40	85	°C

6.4 Thermal Information

over operating free-air temperature range (unless otherwise noted)

THERMAL METRIC⁽¹⁾		TCA8418E	UNIT
		YFP (DSBGA)
		25 PINS
R_θJA	Junction-to-ambient thermal resistance	61.2	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	0.4	°C/W
R_θJB	Junction-to-board thermal resistance	10.6	°C/W
ψ_JT	Junction-to-top characterization parameter	1.0	°C/W
ψ_JB	Junction-to-board characterization parameter	10.6	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	N/A	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

over recommended operating free-air temperature range, V_CC = 1.65 V to 3.6 V (unless otherwise noted)

PARAMETER		TEST CONDITIONS			V_CC	MIN	TYP	MAX	UNIT
V_IK	Input diode clamp voltage	I_I = –18 mA			1.65 V to 3.6 V	–1.2			V
V_PORR	Power-on reset voltage, V_CC rising	V_I = V_CCP or GND, I_O = 0			1.65 V to 3.6 V	1.03		1.43	V
V_PORF	Power-on reset voltage, V_CC falling	V_I = V_CCP or GND, I_O = 0			1.65 V to 3.6 V	0.76		1.15	V
V_OH	ROW0–7, COL0–9 high-level output voltage	I_OH = –1 mA			1.65 V	1.25			V
		I_OH = –8 mA			1.65 V	1.2
					2.3 V	1.8
					3 V	2.6
		I_OH = –10 mA			1.65 V	1.1
					2.3 V	1.7
					3 V	2.5
V_OL	ROW0–7, COL0–9 low-level output voltage	I_OL = 1 mA			1.65 V			0.4	V
		I_OL = 8 mA			1.65 V			0.45
					2.3 V			0.25
					3 V			0.25
		I_OL = 10 mA			1.65 V			0.6
					2.3 V			0.3
					3 V			0.25
I_OL	SDA	V_OL = 0.4 V			1.65 V to 3.6 V	3			mA
I_OL	INT and CAD_INT	V_OL = 0.4 V			1.65 V to 3.6 V	3			mA
I_I	SCL, SDA, ROW0–7, COL0–9, RESET	V_I = V_CCI or GND			1.65 V to 3.6 V			1	μA
R_INT	Internal pullup resistor value	ROW0–7, COL0–9					55		kΩ
I_CC_{Supply Voltage}		V_I on SDA, ROW0–7, COL0–9 = V_CC or GND, I_O = 0, I/O = inputs,	f_SCL = 0 kHz	Oscillator OFF	1.65 V to 3.6 V			13	μA
			f_SCL = 0 kHz	Oscillator ON	1.65 V to 3.6 V			18
			f_SCL = 400 kHz	1 key press	1.65 V			15
			f_SCL = 400 kHz		3.6 V			30
			f_SCL = 1 MHz		1.65 V			15
			f_SCL = 1 MHz		3.6 V			40
			f_SCL = 400 kHz	GPI low (pullup enable)⁽¹⁾	1.65 V to 3.6 V			115
			f_SCL = 1 MHz	GPI low (pullup enable)⁽¹⁾				125
			f_SCL = 400 kHz	GPI low (pullup disable)				25
			f_SCL = 1 MHz	GPI low (pullup disable)				35
			f_SCL = 400 kHz	1 GPO active				115
			f_SCL = 1 MHz	1 GPO active				125
C_I	SCL	V_I = V_CC or GND			1.65 V to 3.6 V		6	8	pF
C_io	SDA	V_IO = V_CC or GND			1.65 V to 3.6 V		10	12.5	pF
C_io	ROW0–7, COL0–9	V_IO = V_CC or GND			1.65 V to 3.6 V		5	6	pF

(1) Assumes that one GPIO is enabled.

6.6 I²C Interface Timing Requirements

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 16)

		STANDARD MODE I²C BUS		FAST MODE I²C BUS		FAST MODE PLUS (FM+) I²C BUS		UNIT
		MIN	MAX	MIN	MAX	MIN	MAX	UNIT
f_scl	I²C clock frequency	0	100	0	400	0	1000	kHz
t_sch	I²C clock high time	4		0.6		0.26		μs
t_scl	I²C clock low time	4.7		1.3		0.5		μs
t_sp	I²C spike time		50		50		50	ns
t_sds	I²C serial data setup time	250		100		50		ns
t_sdh	I²C serial data hold time	0		0		0		ns
t_icr	I²C input rise time		1000	20 + 0.1C_b ⁽¹⁾	300		120	ns
t_icf	I²C input fall time		300	20 + 0.1C_b⁽¹⁾	300		120	ns
t_ocf	I²C output fall time; 10 pF to 400 pF bus		300	20 + 0.1C_b ⁽¹⁾	300		120	μs
t_buf	I²C bus free time between Stop and Start	4.7		1.3		0.5		μs
t_sts	I²C Start or repeater Start condition setup time	4.7		0.6		0.26		μs
t_sth	I²C Start or repeater Start condition hold time	4		0.6		0.26		μs
t_sps	I²C Stop condition setup time	4		0.6		0.26		μs
t_vd(data)	Valid data time; SCL low to SDA output valid		1		0.9		0.45	μs
t_vd(ack)	Valid data time of ACK condition; ACK signal from SCL low to SDA (out) low		1		0.9		0.45	μs

(1) C_b = total capacitance of one bus line in pF

6.7 Reset Timing Requirements for Standard Mode, Fast Mode, Fast Mode Plus (FM+) I²C Bus

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 19)

		MIN	UNIT
t_W	Reset pulse duration	120⁽¹⁾	μs
t_REC	Reset recovery time	120⁽¹⁾	μs
t_RESET	Time to reset	120⁽¹⁾	μs

(1) The GPIO debounce circuit uses each GPIO input which passes through a two-stage register circuit. Both registers are clocked by the same clock signal, presumably free-running, with a nominal period of 50 μs. When an input changes state, the new state is clocked into the first stage on one clock transition. On the next same-direction transition, if the input state is still the same as the previously clocked state, the signal is clocked into the second stage, and then on to the remaining circuits. Since the inputs are asynchronous to the clock, it will take anywhere from zero to 50 μs after the input transition to clock the signal into the first stage. Therefore, the total debounce time may be as long as 100 μs. Finally, to account for a slow clock, the spec further guard-banded at 120 μs.

6.8 Switching Characteristics for Standard Mode, Fast Mode, Fast Mode Plus (FM+) I²C Bus

PARAMETER			FROM	TO	MIN	MAX	UNIT
t_IV	Interrupt valid time	Key event or Key unlock or Overflow	ROW0–7, COL0–9	INT	20	60	μs
		GPI_INT with Debounce_DIS_Low			40	120
		GPI_INT with Debounce_DIS_High			10	30
		CAD_INT		INT, CAD_INT	20	60
t_IR	Interrupt reset delay time		SCL	INT		200	ns
t_IR	Interrupt reset delay time		SCL	CAD_INT		200	ns
t_PV	Output data valid		SCL	ROW0–7, COL0–9		400	ns
t_PS	Input data setup time		P port	SCL	0		ns
t_PH	Input data hold time		P port	SCL	300		ns